DATASHEET HFA3102. Features. Ordering Information. Applications. Pinout/Functional Diagram. Dual Long-Tailed Pair Transistor Array

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Transcription:

DATASHEET HFA312 Dual Long-Tailed Pair Transistor Array The HFA312 is an all NPN transistor array configured as dual differential amplifiers with tail transistors. Based on Intersil bonded wafer UHF-1 SOI process, this array achieves very high f T (1GHz) while maintaining excellent h FE and V BE matching characteristics over temperature. Collector leakage currents are maintained to under.1na. Ordering Information PART NUMBER TEMP. RANGE ( C) Pinout/Functional Diagram HFA312 (SOIC) TOP VIEW PACKAGE HFA312B9 - to 5 1 Ld SOIC Tape and Reel HFA312BZ (Note) HFA312BZ9 (Note) - to 5 1 Ld SOIC (Pb-free) - to 5 1 Ld SOIC Tape and Reel (Pb-free) PKG. DWG. # M1.15 M1.15 M1.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. 1 13 11 1 9 Q 1 Q 2 Q Features FN335 Rev.5. High Gain-Bandwidth Product (f T )............. 1GHz High Power Gain-Bandwidth Product............ 5GHz High Current Gain (h FE )....................... 7 Noise Figure (Transistor)..................... 3.5dB Low Collector Leakage Current.............. <.1nA Excellent h FE and V BE Matching Pin-to-Pin to UPA12G Pb-Free Plus Anneal Available (RoHS Compliant) Applications Single Balanced Mixers Wide Band Amplification Stages Differential Amplifiers Multipliers Automatic Gain Control Circuits Frequency Doublers, Tripplers Oscillators Constant Current Sources Wireless Communication Systems Radio and Satellite Communications Fiber Optic Signal Processing High Performance Instrumentation Q 3 Q Q 5 1 2 3 5 7 FN335 Rev.5. Page 1 of 7

Absolute Maximum Ratings T A = 25 C V CEO Collector to Emitter Voltage.......................V V CBO Collector to Base Voltage........................V V EBO Emitter to Base Voltage.........................V I C, Collector Current.................................3mA Operating Conditions Temperature Range.......................... - C to 5 C Thermal Information Thermal Resistance (Typical, Note 1) JA ( C/W) SOIC Package............................. Maximum Power Dissipation at 75 Any One Transistor................................25W Maximum Junction Temperature (Die).................... 175 C Maximum Junction Temperature (Plastic Package)........ 15 C Maximum Storage Temperature Range.......... -5 C to 15 C Maximum Lead Temperature (Soldering 1s)............. 3 C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = 25 C SYMBOLS PARAMETER TEST CONDITIONS (NOTE 2) TEST LEVEL ALL GRADES MIN TYP MAX UNITS V (BR)CBO Collector-to-Base Breakdown Voltage (Q 1, Q 2, Q, and Q 5 ) I C = 1 A, I E = A 1 - V V (BR)CEO Collector-to-Emitter Breakdown Voltage (Q 1 thru Q ) I C = 1 A, I B = A - V V (BR)EBO Emitter-to-Base Breakdown Voltage (Q 3 and Q ) I E = 5 A, I C = A 5.5 - V I CBO Collector Cutoff Current (Q 1, Q 2, Q, and Q 5 ) V CB = 5V, I E = A -.1 1 I EBO Emitter Cutoff Current (Q 3 and Q ) V EB = 1V, I C = A - - 1 h FE DC Current Gain (Q 1 thru Q ) I C = 1mA, A 7 - - C CB Collector-to-Base Capacitance V CB = 5V, f = 1MHz B - 3 - ff C EB Emitter-to-Base Capacitance V EB =, f = 1MHz B - 2 - ff f T Current Gain-Bandwidth Product I C = 1mA, V CE = 5V C - 1 - GHz f MAX Power Gain-Bandwidth Product I C = 1mA, V CE = 5V C - 5 - GHz G NFMIN Available Gain at Minimum Noise Figure I C = 3mA, NF MIN Minimum Noise Figure I C = 3mA, NF 5 5 Noise Figure I C = 3mA, f =.5GHz C - 17.5 - db f = 1.GHz C -. - db f =.5GHz C - 1. - db f = 1.GHz C - 2.1 - db f =.5GHz C - 3.3 - db f = 1.GHz C - 3.5 - db h FE1 /h FE2 DC Current Gain Matching (Q 1 and Q 2, Q and Q 5 ) I C = 1mA, A.9 1. 1.1 - V OS Input Offset Voltage (Q 1 and Q 2 ), (Q and Q 5 ) I OS Input Offset Current (Q 1 and Q 2 ), (Q and Q 5 ) I C = 1mA, A - 1.5 5 mv I C = 1mA, A - 5 25 A dv OS /dt I TRENCH- LEAKAGE Input Offset Voltage TC (Q 1 and Q 2, Q and Q 5 ) Collector-to-Collector Leakage (Pin, 7, 13, and 1) I C = 1mA, C -.5 - V/ C V TEST = 5V B -.1 - na NOTE: 2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only FN335 Rev.5. Page 2 of 7

PSPICE Model for a Single Transistor.Model NUHFARRY NPN + ( IS= 1.E-1 XTI= 3.E+ EG= 1.11E+ VAF= 7.2E+1 + VAR=.5E+ BF= 1.3E+2 ISE= 1.E-19 NE= 1.E+ + IKF= 5.E-2 XTB=.E+ BR= 1.E+1 ISC= 1.5E-1 + NC= 1.E+ IKR= 5.E-2 RC= 1.1E+1 CJC= 3.9E-13 + MJC= 2.E-1 VJC= 9.7E-1 FC= 5.E-1 CJE= 2.E-13 + MJE= 5.1E-1 VJE=.9E-1 TR=.E-9 TF= 1.51E- + ITF= 3.5E-2 XTF= 2.3E+ VTF= 3.5E+ PTF=.E+ + XCJC= 9.E-1 CJS= 1.9E-13 VJS= 9.92E-1 MJS=.E+ + RE= 1.E+ RB= 5.7E+1 RBM= 1.97E+ KF=.E+ + AF= 1.E+) Common Emitter S-Parameters V CE = 5V and I C = 5mA FREQ. (Hz) S 11 PHASE(S 11 ) S PHASE(S ) S 21 PHASE(S 21 ) S 22 PHASE(S 22 ) 1.E+.3379-11.773 1.191E-2 7.5 11.722 1.57.9733-11.59 2.E+.79177-22.29 2.957E-2.355 1.5177 157.97.93993-21.35 3.E+.73911-32.5 3.7529E-2 59.51 9.75379 1.3. -3.51.E+.7211-1.71.57213E-2 51.91.91 1.31.799-3.11 5.E+.1 -.237 5.1917E-2 5.53.1511 133.59.7333 -.599.E+.557-5.27 5.5993E-2.21 7.359 7.2.7392-9.937 7.E+.5133-59.12.957E-2 35.22.97 3.12.2211-5.3777.E+.531-3.3.27213E-2 32.159.1175 119.7.57729-5.122 9.E+.223-7.313.7713E-2 29.73 5.133 115.571.53952-1.257 1.E+9.393-7.93.3791E-2 2.5 5.175 1.55.535-3.97 1.1E+9.332-73.9591.75932E-2 2.197.791 19.913.73 -.311 1.2E+9.3359-7.25.57937E-2 22.21.55 17.57.5591 -.372 1.3E+9.322155-79.2.93737E-2 2.535.15997 15.72.35-7.195 1.E+9.332-1.25 7.32E-2 19.293 3.95 13.57.1772-71.31 1.5E+9.252-3.2 7.571E-2 17.9 3.577 11.9.323-73.31 1.E+9.271-5.1723 7.1133E-2 1.93 3.577 1.22.39735-7.9 1.7E+9.25359 -.9292 7.13717E-2 15.13 3.277 9.795.35-75.93 1.E+9.22 -.5759 7.17231E-2 1.37 3.1197 97.37.3797-77.5 1.9E+9.23559-9.5 7.199E-2 13.59 2.997 9.1533.33195-7. 2.E+9.225923-91.5925 7.219757E-2.7319 2.99 9.9515.3523-79.1377 2.1E+9.2175-92.93 7.23927E-2 11.92 2.23 93.15.3511 -.93 2.2E+9.293-9.37 7.25E-2 11.291 2.5573 92.7373.32 -.992 2.3E+9.217-95.5713 7.279E-2 1. 2.537 91.797.32599-1.557 2.E+9.19939-9.73 7.22977E-2 1.53 2.3592 9.7271.3395-2.2 2.5E+9.177-97.9395 7.2937E-2 9.92 2.275 9.7.3392-3.719 2.E+9.13-99.53 7.3393E-2.99 2.3.775.3392 -.237 2.7E+9.1777-1. 7.311157E-2.7753 2.1322.2.33351 -.971 2.E+9.17299-11.15 7.31117E-2.13 2.293 7.155.33299-5.53 2.9E+9.139-12.152 7.3217E-2 7.571 1.927.33.33179 -.371 3.E+9.12-13.11 7.32923E-2 7.12 1.955 5.5.3312-7.51 FN335 Rev.5. Page 3 of 7

V CE = 5V and I C = 1mA FREQ. (Hz) S 11 PHASE(S 11 ) S PHASE(S ) S 21 PHASE(S 21 ) S 22 PHASE(S 22 ) 1.E+.721-1.319 1.27392E-2 75.177 15.73 15.227.95992-1.2 2.E+.73-31.29 2.323E-2 2.91 13.91 152.5.232-2.957 3.E+.2-3.73 3.132521E-2 52.591.397 11.15.791-37.3172.E+.5317-5.2 3.1579E-2.519 1.9257 132.57.792-5.53 5.E+.71795-2.3.57E-2 3.23 9.2995 5.71.331-51.77.E+.215-9.359.31292E-2 33.35.53559.37.5729-5.72 7.E+.37991-75.2.9971E-2 29.7 7.2375 11.5.513 -.59.E+.3593 -.3.311E-2 2.3755.23 1.39.797-3.5 9.E+.31731 -.2.729E-2 23.1.22797 19.35.2915 -.9 1.E+9.293 -.31.391E-2 21.751 5.957 1.771.15 -.7193 1.1E+9.273-92.52.515E-2 2.7 5.23257 1.51.3921-7.29 1.2E+9.2572-95.733.9571E-2 1.522.373 12.532.37321-72.299 1.3E+9.223-9.7555.923E-2 17.255.971 1.759.357-73.72 1.E+9.22991-11.551.97215E-2 1.15.195 99.12.39-75.32 1.5E+9.219152-1.15.9993E-2 15.1915 3.9355 97.72.33397-7.2 1.E+9.2977-1.577 5.1773E-2 1.39 3.723 9.329.32512-77.377 1.7E+9.21539-1.51 5.3591E-2 13. 3.92 95.15.31779-7.2 1.E+9.192-11.9 5.525E-2.911 3.375 93.933.311-79.3715 1.9E+9.177-113.1 5.21E-2.32 3.13919 92.71.39 -.27 2.E+9.157-11.92 5.75E-2 11.151 2.95 91.5.3351-1.135 2.1E+9.1775-11.9 5.59E-2 11.333 2.7 9.7.33-1.957 2.2E+9.172-11.399 5.917E-2 1.97 2.72 9.99.297-2.7 2.3E+9.137 -. 5.1755E-2 1.51 2.2 9.2.297-3.557 2.E+9.15-1.52 5.19E-2 1.1373 2.997.2115.299 -.25 2.5E+9.193-2.99 5.31E-2 9.79 2.39793 7.392.292 -.9533 2.E+9.15239 -.37 5.7E-2 9.9919 2.319.7.291-5. 2.7E+9.1555-5.9 5.1333E-2 9.2175 2.229 5.3.2925 -.3223 2.E+9.152919 -.97 5.13931E-2.9571 2.112 5.91.293 -.922 2.9E+9.15595 -.1 5.151E-2.71595 2.753.39.2959-7.275 3.E+9.13-9.279 5.1597E-2.919 1.992 3.51.293 -.2595 FN335 Rev.5. Page of 7

Typical Performance Curves I C (ma) 1 I B = 15 A I B = A I B = 9 A I B = A h FE 1 1 2 I B = 3 A 2 1 2 3 5 V CE (V) 1-1 1-1 - 1-1 -2 1 I C (A) FIGURE 1. I C vs V CE FIGURE 2. h FE vs I C 1 1-2 1 V CE = 5V I C AND I B (A) 1-1 - 1 - f T (GHz) 1-1 2 1 -... 1. V BE (V) 1-1 -3 1-2 1-1 I C (A) FIGURE 3. GUMMEL PLOT FIGURE. f T vs I C NOISE FIGURE (db). 2. 1. 1.2 1. 3. 1 3. 3. 3.2.5 1. 1.5 2. 2.5 3. FREQUENCY (GHz) S 21 (db) P OUT, OUTPUT POWER (dbm) 2-2 - - - 3rd ORDER INTERCEPT POINT 1dB COMPRESSION POINT 3RD ORDER PRODUCTS V CE = 5V I C = 1mA f = 1GHz -1-3 -2-1 1 P IN, INPUT POWER (dbm) FIGURE 5. GAIN AND NOISE FIGURE vs FREQUENCY FIGURE. P 1dB AND 3RD ORDER INTERCEPT FN335 Rev.5. Page 5 of 7

Die Characteristics PROCESS: UHF-1 DIE DIMENSIONS: 53 mils x 52 mils x 1 mils 13 m x 132 m x 355. m METALLIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: kå.5kå Type: Metal 2: AlCu(2%) Thickness: Metal 2: 1kÅ.kÅ PASSIVATION: Type: Nitride Thickness: kå.5kå SUBSTRATE POTENTIAL (POWERED UP): Floating Metallization Mask Layout HFA312 TOP VIEW 2 1 1 13 3 13 m (53 mils) 11 1 5 7 9 132 m (52 mils) Pad numbers correspond to the 1 pin SOIC pinout. FN335 Rev.5. Page of 7

Small Outline Plastic Packages (SOIC) N INDEX AREA 1 2 3 e D B.25(.1) M C A M E -B- -A- -C- SEATING PLANE A B S H.25(.1) M B A1.1(.) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y1.5M-192. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.3mm (.1 inch) or greater above the seating plane, shall not exceed a maximum value of.1mm (.2 inch). 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 5 o C M1.15 (JEDEC MS--AB ISSUE C) 1 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.532. 1.35 1.75 - A1..9.1.25 - B.13.2.33.51 9 C.75.9.19.25 - D.337.3.55.75 3 E.197.157 3.. e.5 BSC 1.27 BSC - H.22.2 5..2 - h.99.19.25.5 5 L.1.5. 1.27 N 1 1 7 o o o o - Rev. /93 Copyright Intersil Americas LLC 23-25. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN335 Rev.5. Page 7 of 7