VLSI Based Design of Low Power and Linear CMOS Temperature Sensor

Similar documents
A 23 nw CMOS ULP Temperature Sensor Operational from 0.2 V

DESIGN AND ANALYSIS OF SUB 1-V BANDGAP REFERENCE (BGR) VOLTAGE GENERATORS FOR PICOWATT LSI s.

A CMOS TEMPERATURE SENSOR WITH -60OC TO 150OC SENSING RANGE AND ±1.3OC INACCURACY

Sensors and Actuators A: Physical

A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity

NOVEL OSCILLATORS IN SUBTHRESHOLD REGIME

A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor

EEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis

Design and Implementation of less quiescent current, less dropout LDO Regulator in 90nm Technology Madhukumar A S #1, M.

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs

Low Power Design of Successive Approximation Registers

PERFORMANCE CHARACTERISTICS OF EPAD PRECISION MATCHED PAIR MOSFET ARRAY

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852

Sub-threshold Leakage Current Reduction Using Variable Gate Oxide Thickness (VGOT) MOSFET

Total reduction of leakage power through combined effect of Sleep stack and variable body biasing technique

Low Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

A Study on the Characteristics of a Temperature Sensor with an Improved Ring Oscillator

LOW POWER FOLDED CASCODE OTA

Characterization of Variable Gate Oxide Thickness MOSFET with Non-Uniform Oxide Thicknesses for Sub-Threshold Leakage Current Reduction

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407

Keywords - Analog Multiplier, Four-Quadrant, FVF Differential Structure, Source Follower.

DESIGN OF ON CHIP TEMPERATURE MONITORING IN 90NM CMOS

A NEW APPROACH FOR DELAY AND LEAKAGE POWER REDUCTION IN CMOS VLSI CIRCUITS

Ultra-low Power Temperature Sensor

PROCESS and environment parameter variations in scaled

INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010

Current Mirrors. Current Source and Sink, Small Signal and Large Signal Analysis of MOS. Knowledge of Various kinds of Current Mirrors

Design of a Voltage Reference based on Subthreshold MOSFETS

Leakage Power Reduction for Logic Circuits Using Variable Body Biasing Technique

A Nano-Watt MOS-Only Voltage Reference with High-Slope PTAT Voltage Generators

Low Voltage SC Circuit Design with Low - V t MOSFETs

Low voltage, low power, bulk-driven amplifier

High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair

Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits

Design of Low-Dropout Regulator

PRECISION N-CHANNEL EPAD MOSFET ARRAY DUAL HIGH DRIVE NANOPOWER MATCHED PAIR

AnAdderwithNovelPMOSandNMOSforUltraLowPowerApplicationsinDeepSubmicronTechnology

A Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier. Strong inversion operation stops a proposed compact 3V power-efficient

An Ultra-Low Power CMOS PTAT Current Source

Introduction to VLSI ASIC Design and Technology

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:

Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation

LOW CURRENT REFERENCES WITH SUPPLY INSENSITIVE BIASING

A Low Dropout Voltage Regulator with Enhanced Transconductance Error Amplifier and Small Output Voltage Variations

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

Design & Analysis of Low Power Full Adder

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS

Circuit Seed Overview

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

Linear voltage to current conversion using submicron CMOS devices

LOW VOLTAGE ANALOG IC DESIGN PROJECT 1. CONSTANT Gm RAIL TO RAIL INPUT STAGE DESIGN. Prof. Dr. Ali ZEKĐ. Umut YILMAZER

DESIGN ANALYSIS AND COMPARATIVE STUDY OF RF RECEIVER FRONT-ENDS IN 0.18-µM CMOS

Design of a Capacitor-less Low Dropout Voltage Regulator

Investigation on Performance of high speed CMOS Full adder Circuits

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

A Survey of the Low Power Design Techniques at the Circuit Level

Sensors & Transducers Published by IFSA Publishing, S. L.,

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage

UNLIKE traditional temperature sensors that utilize offchip

Lecture Wrap up. December 13, 2005

DESIGN AND ANALYSIS OF LOW POWER CHARGE PUMP CIRCUIT FOR PHASE-LOCKED LOOP

A Resistorless CMOS Non-Bandgap Voltage Reference

6. Field-Effect Transistor

Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs)

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

ANALYSIS AND DESIGN OF HIGH CMRR INSTRUMENTATION AMPLIFIER FOR ECG SIGNAL ACQUISITION SYSTEM USING 180nm CMOS TECHNOLOGY

Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC

Design of a Low Power Current Steering Digital to Analog Converter in CMOS

Robust Ultra-Low Power Sub-threshold DTMOS Logic Λ

Study of Differential Amplifier using CMOS

Low Power Design for Systems on a Chip. Tutorial Outline

Design of low power SRAM Cell with combined effect of sleep stack and variable body bias technique

Leakage Diminution of Adder through Novel Ultra Power Gating Technique

DIGITAL VLSI LAB ASSIGNMENT 1

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Layout Design of LC VCO with Current Mirror Using 0.18 µm Technology

DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs

POWER-MANAGEMENT circuits are becoming more important

Lecture-45. MOS Field-Effect-Transistors Threshold voltage

LOW VOLTAGE INTEGRATED CONVERTER FOR WASTE HEAT THEREMOELECTRIC HARVESTERS

ZIGZAG KEEPER: A NEW APPROACH FOR LOW POWER CMOS CIRCUIT

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

Figure 1 Typical block diagram of a high speed voltage comparator.

An accurate track-and-latch comparator

Design and Analysis of High Gain Differential Amplifier Using Various Topologies

Comparison between Analog and Digital Current To PWM Converter for Optical Readout Systems

Design cycle for MEMS

Read/Write Stability Improvement of 8T Sram Cell Using Schmitt Trigger

DAT175: Topics in Electronic System Design

A CMOS CURRENT CONTROLLED RING OSCILLATOR WITH WIDE AND LINEAR TUNING RANGE

Short Channel Bandgap Voltage Reference

Analog IC Design. Lecture 1,2: Introduction & MOS transistors. Henrik Sjöland. Dept. of Electrical and Information Technology

EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05

Department of Electrical Engineering IIT Madras

Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique

AS high-end smartphones and tablets become smaller and

DESIGN AND SIMULATION OF A HIGH PERFORMANCE CMOS VOLTAGE DOUBLERS USING CHARGE REUSE TECHNIQUE

Transcription:

VLSI Based Design of Low Power and Linear CMOS Temperature Sensor Poorvi Jain 1, Pramod Kumar Jain 2 1 Research Scholar (M.Teh), Department of Electronics and Instrumentation,SGSIS, Indore 2 Associate Professor, Department of Electronics and Instrumentation, SGSIS, Idore E-mail- pjpoorvijain1@gmail.com Abstract Complementary Metal Oxide Semiconductor (CMOS) temperature sensor is introduced in this paper which aims at developing the MOSFET as a temperature sensing element operating in sub-threshold region by using dimensional analysis and numerical optimization techniques A linear CMOS temperature to voltage converter is proposed which focuses on temperature measurement using the difference between the gate-source voltages of transistors that is proportional to absolute temperature with low power. This proposed CMOS temperature sensor is able to measure the temperature range from 0 o C to 120 o C. A comparative study is made between the temperature sensors based on their aspect ratio under the implementation of UMC 180nm CMOS process with single rail power supply of 600mV. Keywords Aspect ratio, CMOS-Complementary Metal Oxide Semiconductor, MOSFET-Metal Oxide Semiconductor Field Effect Transistor, Sub-threshold,Temperature sensor, Low power, Linearity. INTRODUCTION An important issue for powerful, high-speed computing systems (containing microprocessor cores and high speed DRAM) is thermal management. This is of special concern with laptops and other portable computing devices where the heat sinks and/or fans can only help dissipate the heat to a limited degree. This makes variations in clock frequency and/or variation in modes of device operation for DRAM, Flash, and other systems necessary. On-chip smart CMOS temperature sensors have been commonly used for thermal management in these applications. The main considering factors of temperature sensor are as follow: Power : In VLSI implementation many small devices are incorporated resulting into higher and higher level of integration causing too much of heat dissipation. So there is a need of reducing power and thereby also reducing the production cost. For this purpose the power consumption must be in nanowatt. Area : Series connected MOSFET's used for current sink increases the die area of the design, also the sizing of transistor plays an important role in deciding the chip area. The area should be small approximately 0.002m 2. Start-up circuit: Start-up circuit is required in the design if the transient response of the sensor takes a significant amount of time in reaching the steady state. If steady state time is less than 200ms in the worst case then it eliminates the necessity to start-up circuit. As the CMOS technology scales down, the supply voltage also scales down from one generation to the next. It becomes difficult to guarantee that all the transistors work in saturation as the supply voltage drops.therefore, the traditional temperature sensor configuration is not suitable for ultra low voltage applications for that reason the sensor should incorporate some modifications. This modification can be brought by making MOS transistors to work in sub-threshold region. This paper presents a nanowatt integrated temperature sensor for ultra-low power applications such as battery powered portable devices are designed and simulated using Cadence analog and digital system design tools UMC 180nm CMOS technology. Ultra-low power consumption is achieved through the use of sub-threshold ( also known as weak inversion) MOS operation. The transistor are used in this domain because the current here is exponentially dependent on the control voltages of the MOSFET and they draw small currents so as to reduce power consumption. The sensor sinks current in nano-amperes from a single power supply of 0.6V and its power consumption is in nanowatt. The performance of the sensor is highly linear in the range of 0 120 0 C. 96

PROPOSED SCHEME The proposed CMOS temperature sensor as shown in Fig 1 consists of main three blocks: Fig 1. Circuit diagram of CMOS temperature sensor (i) Current source sub-circuit: Analog circuits incorporate current references which are self biasing circuit. Such references are dc quantities that exhibit little dependence on supply and process parameters and a well defined dependence on the (ii) Temperature variable sub-circuit: The temperature variable sub-circuit consists of three couples of serially connected transistors operating in sub-threshold region. It accepts current through PMOS current mirrors current mirror which gives a replica ( if necessary, attenuated or amplified ) of a bias or a signal current and produces an output voltage proportional to temperature. (iii) One point calibration sub-circuit: Calibration consists of determining the indication or output of a temperature sensor with respect to that of a standard at a sufficient number of known temperatures so that, with acceptable means of interpolation, the indication or output of the sensor will be known over the entire temperature range of use. After packaging, the sensor is calibrated by measuring its die temperature at reference point using on-chip calibration transistors. METHODOLOGY The sub-threshold drain current I D of a MOSFET is an exponential function of the gate-source voltage V GS and the drain source voltage V DS, and given by[8]: I D = KI 0 exp V GS V TH ηv T 1 exp V DS V T, (1) Where 2 I 0 = μc OX η 1 V T, (2) and K is the aspect ratio (=W/L) of the transistor, μ is the carrier mobility, C OX is the gate-oxide capacitance, V T is the thermal voltage V TH is the threshold voltage of a MOSFET, and η is the sub-threshold slope factor. 97

In the current-source sub-circuit, gate-source voltage V GS9 is equal to the sum of gate-source voltage V GS8 and drain source voltage V DS10 : V GS9 = V DS10 + V GS8 (3) V DS10 = V GS9 V GS8 = ηv T In K 8 K9 (4) M 10 is operated in the sub-threshold region, so trans-conductance G DS10 is obtained by using Eqs. (1) and (4) G DS10 = I DS 10 V DS 10 = K 10I 0 V T exp V m V TH 10 ηv T V DS 10 V T (5) I = V DS10 G DS10 = ηk 1 I 0 K 9 K 8 η In K 8 K 9 exp V m V TH 10 ηv T (6) As M 10 operates in sub-threshold region (V m - V TH10 <0), I is increased by temperature, so the highest power consumption is in the upper temperature limit.choosing the maximum current is a tradeoff between power consumption and linearity that can be obtained by simulation. In the temperature variable sub-circuit, as M 5, M 6, M 15, M 12, M 16,M 17 are in sub-threshold region, the relation between gate to source voltage and MOS current is equal to Eq. (4). According to Fig.1, currents of M 5, M 12, M 16, M 17 are I and currents of M 6 and M 15 are 3I and 2I. The transistor sizes in our design are simple having the same aspect ratio. V OUT = V GS6 V GS5 + V GS15 V GS12 + V GS16 V GS17 (7) By using Eq. (4) with regard to currents of MOSFETs,output voltage is given by: V OUT = ηv T In I D6I D15 I D16 K 5 K 12 K 17 I D5 I D12 I D17 K 6 K 15 K 16 + V TH (8) By replacing the currents of transistors, output voltage is obtained by: V OUT = ηv T In 6K 5K 12 K 17 K 6 K 15 K 16 + V TH (9) By combination of Eqs. (7) and (9) output voltage can be obtained: V OUT = ηk BT q In 6K 5K 12 K 17 K 6 K 15 K 16 + V TH0 = A T + B (10) where T is absolute temperature, A and B are temperature independent constants. Eq. (10) shows a linear relationship between absolute temperature and output voltage as depicted in Fig 3. Based on aspect ratio (W/L), temperature sensor is designed into two ways: (i) Temperature sensor based on designed W/L ratio : In this design all the MOS transistors used in the circuit diagram are of different width and length. By using large length transistors (L M6-11 >> L min ) the sensitivity to the geometric variations can be minimized and an accurate temperature coefficient is expected. Large transistors also help to reduce the impact on threshold voltage due to random doping fluctuations. Different values of W/L ratio for corresponding MOS transistors is given in the Table I. (ii) Temperature sensor based on minimum W/L ratio : In this design all the MOS transistors used in the circuit diagram are of same width and length. By minimum technology parameter it indicates that width(w) of transistor is 240nm and length(l) of transistor is 180nm. So the equation (10) becomes V OUT = η K BT In 6 + V TH0 = A T + B. q 98

Table I Size of transistors Transistor W/L (µm/µm) M 1 1 (1.5/20) M 2 10 (3/3) M 3 4 (3/3) M 6, M 8, M 10 1 (1/3) M 7 3 (3/3) M 9 4 (3/3) M 11 28 (3/3) M 4, M 5, M 12-14 1 (3/10) M C1, M C2 1 (1/20) Fig 2.The linear relationship of output voltage and temperature of a Fig 3. The linear relationship of output voltage and temperature of a temperature Sensor based on designed W/L Temperature Sensor based on minimum W/L. 99

Sink current versus temperature graph for minimum W/L sensor Fig 5. Sink current versus temperature graph for designed W/L sensor Fig 4. Fig 6. Power versus temperature graph for Temperature Sensor based on designed W/L Fig 7. Power versus temperature graph for Temperature Sensor based on minimum W/L 100

Fig 8. Transient response of designed W/L sensor at temperature 17 0 C Fig 9. Transient response of minimum W/L sensor at temperature 17 0 C Table II Comparison of temperature sensor with previous works Sensor Power supply Power cons. Temp. range Inaccuracy Process [1] 0.5, 1 V 119 nw -10 30 C -0.8 to +1 C 180 nm CMOS [2] 38.5 µw ±2 C 65 nm CMOS [3] 2.7 5.5 V 429 µw -50 125 C ±0.5 C 0.5 µm CMOS [4] 1V 220 nw 0 100 C -1.6 to +3 C 180 nm CMOS [5] 3.0 3.8 V 10 µw 0 100 C -0.7 to +0.9 C 0.35µm CMOS [6] 1V 25 µw +50 125 C -1 to +0.8 C 90 nm CMOS [7] 8.6 µw -55 125 C ±0.4 C 160 nm CMOS [8] 0.6 2.5 V 7 nw +10 120 C ±2 C 180 nm CMOS [This work 0.6 2.5 V 12.5nW 0 120 C ±3 C 180 nm CMOS designed W/L] [This work minimum W/L] 0.6 2.5 V 1.05nW 0 120 C ±6 7 C 180 nm CMOS SIMULATION RESULTS AND DISCUSSION A linear temperature sensor that incorporates semiconductor devices and is capable of high accuracy over a very wide temperature range, such that the voltage drop varies approximately linearly in negative or positive dependence on temperature. The linear relationship of output voltage and temperature at a supply voltage of 600mV is shown in Fig 2 and Fig 3.Temperature Sensor based on 101

designed W/L sinks upto 28nA from a wide range of temperature with a V DD of 600mV is given in Fig 5. As sink current is exponentially increasing with temperature its power consumption also increases. The overall power consumption is more of this temperature design as compared to temperature sensor based on minimum W/L ratio as shown in Fig 4.As the temperature is increased power consumed by the sensor also increases. The power consumption is of merely 12.5nW at 120 0 C is shown in Fig 7.The power consumed is more by this sensor as compared to temperature sensor based on minimum W/L given in Fig 6.At temperature of 15 0 C sustained oscillations are obtained in case of designed aspect ratio temperature sensor, at temperature of 17 0 C smooth response is obtained spontaneously shown in Fig 8 and further on increasing the temperature oscillations are dominant. This proves temperature of 17 0 C is the best temperature for transient response. In case of minimum aspect ratio temperature of 17 0 C is the suitable temperature for transient response given in the Fig 9. The transient response of temperature sensor based on designed W/L is more practically realizable ( similar to unit step response ) as compared to temperature sensor based on minimum W/L. CONCLUSION This research investigate an ultra low power temperature sensor. Tables II and III shows the comparison between the designed sensor with previous works and its performance summary. As the oscillations were profound in the transient response of the temperature sensor, this can be eliminated by using Proportional Integral Derivative controller based on IMC approach so as to get smooth steady state response at a particular temperature. This transient response is helpful in determining the need of start-up circuit. It is required that if steady state time is less than 200ms then there is no need of start -up circuit. As a result, the temperature sensor based on two approaches of aspect ratio are significantly important according to their performances in relative desired characteristics. The layout area of the sensor is shown in the Fig 10 and Fig 11. From area and power point of view temperature sensor based on minimum aspect ratio is preferred whereas considering linearity, temperature error inaccuracy and transient response temperature sensor based on designed aspect ratio is dominant. Table III Performance Summary Parameter temperature sensor based on designed W/L Value temperature sensor based on minimum W/L Value Power Supply 0.6-2.5V 0.6-2.5V Power Consumption 12.5nW @ 120 0 C, 1.05nW @ 120 0 C, Circuit area 0.0076mm 2 0.00013mm 2 Inaccuracy versus temperature 3 0 C 6-7 0 C Inaccuracy versus V DD 0.52 0 C/V 0.47 0 C/V Sensitivity 1.41mV/ 0 C 0.354mV/ 0 C 102

Transient response Stable at 17 0 C Sustained oscillations Sink current 28nA @ 120 0 C, Transconductance 5.005 na/v @ 25 0 C, Transresistance 22.7 MΩ @ 25 0 C, 5nA @ 120 0 C, 0.815 na/v @ 25 0 C, 416.6 MΩ @ 25 0 C, Fig 10. The layout of CMOS temperature sensor based aspect ratio Fig 11. The layout of CMOS temperature sensor based on designed on minimum aspect ratio REFERENCES: [1] Law, M. K., Bermak, A., & Luong, H. C. A. Sub-µW embedded CMOS temperature sensor for RFID food monitoring application. IEEE Journal of Solid-State Circuits, 45(6), 1246 1255, (2010) [2] Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955 Datasheet. On 65 nm Process in the 775-Land LGA Package and Supporting Intel Extended Memory 64 Technology, and Supporting Intel Virtualization Technology, Intel Corp., Document 310306-002,(2006). [3] Pertijs, M. A. P., Niederkorn, A., Xu, M., McKillop, B., Bakker, A., & Huijsing, J. H. A CMOS smart temperature sensor with a 3σ inaccuracy of 0.5 C from -50 to 120 C. IEEE Journal of Solid-State Circuits, 40(2), 454 461. (2005). 103

[4] Lin, Y. S., Sylvester, D., & Blaauw, D. An ultra low power 1 V, 220 nw temperature sensor for passive wireless applications. In Custom Integrated Circuits Conference (CICC). IEEE, pp. 507 510. (2008). [5] Chen, P., Chen, C. C., Tsai, C. C., & Lu, W. F. A time-to digital- converter-based CMOS smart temperature sensor. IEEE Journal of Solid-State Circuits, 40(8), 1642 1648. (2005). [6] M. Sasaki, M. Ikeda, and K. Asada, "A temperature sensor with an inaccuracy of -1/+0.8 o C using 90-nm I-V CMOS for online thermal monitoring of VLSI circuits," IEEE Trans. Semiconductor Manufacturing, Vol. 2 1, No.2, pp.201-20s, May (2005). [7] Souri, K., Chae, Y., Ponomarev, Y., & Makinwa, K. A.. A precision DTMOST-based temperature sensor. In Proceedings of the ESSCIRC (ESSCIRC),pp. 279 282, (2011). [8] Sahafi, Jafar Sobhi, Ziaddin Daie Koozehkanani,"Nanowatt CMOS temperature sensor".analog Integr circ sig process in springer,75:343-348, (2013). [9] Ueno, K., Asai, T., & Amemiya, Y. Low-power temperature- to-frequency converter consisting of sub-threshold CMOS circuits for integrated smart temperature sensors. Sensors and Actuators A Physical, 165, 132 137 (2011). [10] Balachandran, G. K., & Barnett, R. E. A 440-nA true random number generator for passive RFID tags. IEEE Transactions on Circuits and Systems I Regular Papers, 55(11), 3723 3732, (2008). [11] Bruce W. Ohme, Bill J. Johnson, and Mark R. Larson SOI CMOS for Extreme Temperature Applications Honeywell Aerospace, Defense and Space, Honeywell International Plymouth Minnesota USA, (2012). [12] Q. Chen, M. Meterelliyoz, and K. Roy, "A CMOS thermal sensor and its applications in temperature adaptive design," Proc. of the 7th Int'l Symposium on Quality Electronic Design, pp.-24s, (2006). Man kay law, and A Bermak A 405-nw CMOS Temperature sensor based on linear MOS operation IEEE Transaction on Circuits and Systems,vol.56,no,12,December (2009) 104