November 2013 FAN7930B Criical Conducion Mode PFC Conroller Feaures Addiional OVP Deecion Pin V INAbsen Deecion Maximum Swiching Frequency Limiaion Inernal SofSar and Sarup wihou Overshoo Inernal Toal Harmonic Disorion (THD) Opimizer Precise Adjusable Oupu OverVolage Proecion OpenFeedback Proecion and Disable Funcion Zero Curren Deecor (ZCD) 150 μs Inernal Sarup Timer MOSFET OverCurren Proecion (OCP) UnderVolage Lockou wih 3.5 V Hyseresis Low Sarup and Operaing Curren ToemPole Oupu wih High Sae Clamp 500/800 ma Peak Gae Drive Curren 8Pin, SmallOuline Package (SOP) Applicaions Adaper Ballas LCD TV, CRT TV SMPS Descripion The FAN7930B is an acive power facor correcion (PFC) conroller for boos PFC applicaions ha operae in criical conducion mode (CRM). I uses a volagemode PWM ha compares an inernal ramp signal wih he error amplifier oupu o generae a MOSFET urnoff signal. Because he volagemode CRM PFC conroller does no need recified AC line volage informaion, i saves he power loss of an inpu volage sensing nework necessary for a currenmode CRM PFC conroller. FAN7930B provides overvolage proecion (OVP), openfeedback proecion, overcurren proecion (OCP), inpuvolageabsen deecion, and undervolage lockou proecion (UVLO). The addiional OVP pin can be used o shu down he boos power sage when oupu volage exceeds OVP level due o he resisors ha are conneced a INV pin are damaged. The FAN7930B can be disabled if he INV pin volage is lower han 0.45 V and he operaing curren decreases o a very low level. Using a new variable onime conrol mehod, oal harmonic disorion (THD) is lower han in convenional CRM boos PFC ICs. Relaed Resources AN8035 Design Consideraion for Boundary Conducion Mode PFC Using FAN7930 Ordering Informaion Par Number Operaing Temperaure Range Top Mark Package Packing Mehod FAN7930BMX_G 40 o 125 C FAN7930BG 8Lead, SmallOuline Package (SOP) Tape & Reel FAN7930B Rev. 1.0.3
Applicaion Diagram DC OUTPUT Line Filer AC INPUT Vcc FAN7930B 8 Ou VCC 5 CS ZCD INV 3 COMP GND OVP 6 7 4 1 2 Figure 1. Typical Boos PFC Applicaion Inernal Block Diagram ZCD 5 VCC Clamp Circui VREF VBIAS 2.5VREF Inernal Bias VCC H:open rese 8.5 12 VCC VZ VTH(S/S) 8 V CC VTH(ZCD) Resar Tmer fmax Limi Gae Driver VO(MAX) 7 OUT THD Opimized Sawooh Generaor Conrol Range Compensaion S R Q Q INV 1 VREF VREF Sair Sep Sarup wihou Overshoo rese Clamp Circui VIN Absen VCS_LIM 8pF 40kW 4 CS 6 GND COMP 3 OVP 2 VREF INV_open OVP disable 0.35 0.45 VOVP,LH disable disable 2.5 2.675 Thermal Shudown 2.5 2.88 Figure 2. Funcional Block Diagram FAN7930B Rev. 1.0.3 2
Pin Configuraion V CC OUT GND ZCD FAN7930BG 8SOP INV OVP COMP CS Figure 3. Pin Configuraion (Top View) Pin Definiions Pin # 1 INV Name Descripion This pin is he invering inpu of he error amplifier. The oupu volage of he boos PFC converer should be resisively divided o 2.5 V. 2 OVP This pin is used o deec PFC oupu over volage when INV pin informaion is no correc. 3 COMP 4 CS 5 ZCD 6 GND 7 OUT This pin is he oupu of he ransconducance error amplifier. Componens for he oupu volage compensaion should be conneced beween his pin and GND. This pin is he inpu of he overcurren proecion comparaor. The MOSFET curren is sensed using a sensing resisor and he resuling volage is applied o his pin. An inernal RC filer is included o filer swiching noise. This pin is he inpu of he zerocurren deecion (ZCD) block. If he volage of his pin goes higher han 1.5 V, hen goes lower han 1.4 V, he MOSFET is urned on. This pin is used for he ground poenial of all he pins. For proper operaion, he signal ground and he power ground should be separaed. This pin is he gae drive oupu. The peak sourcing and sinking curren levels are 500 ma and 800 ma, respecively. For proper operaion, he sray inducance in he gae driving pah mus be minimized. 8 V CC This is he IC supply pin. IC curren and MOSFET drive curren are supplied using his pin. FAN7930B Rev. 1.0.3 3
Absolue Maximum Raings Sresses exceeding he absolue maximum raings may damage he device. The device may no funcion or be operable above he recommended operaing condiions and sressing he pars o hese levels is no recommended. In addiion, exended exposure o sresses above he recommended operaing condiions may affec device reliabiliy. The absolue maximum raings are sress raings only. Symbol Parameer Min. Max. Uni V CC Supply Volage V Z V I OH, I OL Peak Drive Oupu Curren 800 500 ma I CLAMP Driver Oupu Clamping Diodes V O>V CC or V O<0.3 V 10 10 ma I DET Deecor Clamping Diodes 10 10 ma V IN Error Amplifier Inpu, Oupu, OVP Inpu, ZCD Pins (1) 0.3 8.0 CS Inpu Volage (2) 10.0 6.0 T J Operaing Juncion Temperaure 150 C T A Operaing Temperaure Range 40 125 C T STG Sorage Temperaure Range 65 150 C ESD Elecrosaic Discharge Capabiliy Human Body Model, JESD22A114 2.5 Charged Device Model, JESD22C101 2.0 Noes: 1. When his pin is supplied by exernal power sources by acciden, is maximum allowable curren is 50 ma. 2. In case of DC inpu, he accepable inpu range is 0.3 V~6 V: wihin 100 ns 10 V~6 V is accepable, bu elecrical specificaions are no guaraneed during such a shor ime. V kv Thermal Impedance Symbol Parameer Min. Max. Uni JA Thermal Resisance, JuncionoAmbien (3) 150 C/W Noe: 3. Regarding he es environmen and PCB ype, please refer o JESD512 and JESD5110. FAN7930B Rev. 1.0.3 4
Elecrical Characerisics V CC = 14 V and T A = 40 C~125 C, unless oherwise specified. Symbol Parameer Condiions Min. Typ. Max. Uni V CC Secion V START Sar Threshold Volage V CC Increasing 11 12 13 V V STOP Sop Threshold Volage V CC Decreasing 7.5 8.5 9.5 V HY UVLO UVLO Hyseresis 3.0 3.5 4.0 V V Z Zener Volage I CC=20 ma 20 22 24 V V OP Recommended Operaing Range 13 20 V Supply Curren Secion I START Sarup Supply Curren V CC=V START0.2 V 120 190 µa I OP Operaing Supply Curren Oupu No Swiching 1.5 3.0 ma I DOP Dynamic Operaing Supply Curren 50 khz, C I=1 nf 2.5 4.0 ma I OPDIS Operaing Curren a Disable V INV=0 V 90 160 230 µa Error Amplifier Secion V REF1 Volage Feedback Inpu Threshold1 T A=25 C 2.465 2.500 2.535 V V REF1 Line Regulaion V CC=14 V~20 V 0.1 10.0 mv V REF2 Temperaure Sabiliy of V REF1 (4) 20 mv I EA,BS Inpu Bias Curren V INV=1 V~4 V 0.5 0.5 µa I EAS,SR Oupu Source Curren V INV=V REF 0.1 V 12 µa I EAS,SK Oupu Sink Curren V INV=V REF 0.1 V 12 µa V EAH Oupu Upper Clamp Volage V INV=1 V, V CS=0 V 6.0 6.5 7.0 V V EAZ Zero Duy Cycle Oupu Volage 0.9 1.0 1.1 V g m Transconducance (4) 90 115 140 µmho Maximum OnTime Secion ON,MAX1 Maximum OnTime Programming 1 T A=25 C, V ZCD=1 V 35.5 41.5 47.5 µs ON,MAX2 Maximum OnTime Programming 2 CurrenSense Secion V CS Curren Sense Inpu Threshold Volage Limi T A=25 C, I ZCD=0.469 ma 11.2 13.0 14.8 µs 0.7 0.8 0.9 V I CS,BS Inpu Bias Curren V CS=0~1 V 1.0 0.1 1.0 µa (4) dv/d=1 V/100 ns, CS,D Curren Sense Delay o Oupu from 0 V o 5 V 350 500 ns Coninued on he following page FAN7930B Rev. 1.0.3 5
Elecrical Characerisics V CC = 14 V and T A = 40 C~125 C, unless oherwise specified. Symbol Parameer Condiions Min. Typ. Max. Uni ZeroCurren Deec Secion V ZCD Inpu Volage Threshold (4) 1.35 1.50 1.65 V HY ZCD Deec Hyseresis (4) 0.05 0.10 0.15 V V CLAMPH Inpu High Clamp Volage I DET=3 ma 5.5 6.2 7.5 V V CLAMPL Inpu Low Clamp Volage I DET=3 ma 0 0.65 1.00 V I ZCD,BS Inpu Bias Curren V ZCD=1 V~5 V 1.0 0.1 1.0 µa I ZCD,SR Source Curren Capabiliy (4) T A=25 C 4 ma I ZCD,SK Sink Curren Capabiliy (4) T A=25 C 10 ma ZCD,D Oupu Secion Maximum Delay From ZCD o Oupu TurnOn (4) dv/d=1 V/100 ns, from 5 V o 0 V 100 200 ns V OH Oupu Volage High I O=100 ma, T A=25 C 9.2 11.0 12.8 V V OL Oupu Volage Low I O=200 ma, T A=25 C 1.0 2.5 V RISE Rising Time (4) C IN=1 nf 50 100 ns FALL Falling Time (4) C IN=1 nf 50 100 ns V O,MAX Maximum Oupu Volage V CC=20 V, I O=100 µa 11.5 13.0 14.5 V V O,UVLO Oupu Volage wih UVLO Acivaed V CC=5 V, I O=100 µa 1 V Resar / Maximum Swiching Frequency Limi Secion RST Resar Timer Delay 50 150 300 µs f MAX Maximum Swiching Frequency (4) 250 300 350 khz SofSar Timer Secion SS Inernal SofSof (4) 3 5 7 ms Proecions V OVP,INV OVP Threshold Volage a INV Pin T A=25 C 2.620 2.675 2.730 V HY OVP,INV OVP Hyseresis a INV Pin T A=25 C 0.120 0.175 0.230 V V OVP,OVP OVP Threshold Volage a OVP Pin T A=25 C 2.740 2.845 2.960 V HY OVP,OVP OVP Hyseresis a OVP Pin T A=25 C 0.345 V V EN Enable Threshold Volage 0.40 0.45 0.50 V HY EN Enable Hyseresis 0.05 0.10 0.15 V T SD Thermal Shudown Temperaure (4) 125 140 155 C T HYS Hyseresis Temperaure of TSD (4) 60 C Noe: 4. These parameers, alhough guaraneed by design, are no producion esed. FAN7930B Rev. 1.0.3 6
Comparison of FAN7530 and FAN7930B Funcion FAN7530 FAN7930B FAN7930B Advanages OVP Pin None Inegraed Frequency Limi None Inegraed No Exernal Circui for addiional OVP Reducion of Power Loss and BOM Cos Caused by Addiional OVP Circui Abnormal CCM Operaion Prohibied Abnormal Inducor Curren Accumulaion Can Be Prohibied V INAbsen Deecion None Inegraed Increase Sysem Reliabiliy by Tesing for Inpu Supply Volage Guaranee Sable Operaion a Shor Elecric Power Failure SofSar and Sarup wihou Overshoo None Inegraed Reduce Volage and Curren Sress a Sarup Eliminae Audible Noise Due o Unwaned OVP Triggering Conrol Range Compensaion None Inegraed Can Avoid Burs Operaion a Ligh Load and High Inpu Volage Reduce Probabiliy of Audible Noise Due o Burs Operaion THD Opimizer Exernal Inernal No Exernal Resisor is Needed TSD None 140 C wih 60 C Hyseresis Sable and Reliable TSD Operaion Converer Temperaure Range Limied Range Comparison of FAN7930C and FAN7930B Funcion FAN7930C FAN7930B Remark RDY Pin Inegraed None OVP Pin None Inegraed User Choice for he Use of Number #2 Pin FAN7930B Rev. 1.0.3 7
Typical Performance Characerisics Figure 4. Volage Feedback Inpu Threshold 1 (V REF1) vs. T A Figure 5. Sar Threshold Volage (V START) vs. T A Figure 6. Sop Threshold Volage (V STOP) vs. T A Figure 7. Sarup Supply Curren (I START) vs. T A Figure 8. Operaing Supply Curren (I OP) vs. T A Figure 9. Oupu Upper Clamp Volage (V EAH) vs. T A FAN7930B Rev. 1.0.3 8
Typical Performance Characerisics Figure 10. Zero Duy Cycle Oupu Volage (V EAZ) vs. T A Figure 11. Maximum OnTime Program 1 ( ON,MAX1) vs. T A Figure 12. Maximum OnTime Program 2 ( ON,MAX2) vs. T A Figure 13. Curren Sense Inpu Threshold Volage Limi (V CS) vs. T A Figure 14. Inpu High Clamp Volage (V CLAMPH) vs. T A Figure 15. Inpu Low Clamp Volage (V CLAMPL) vs. T A FAN7930B Rev. 1.0.3 9
Typical Performance Characerisics Figure 16. Oupu Volage High (V OH) vs. T A Figure 17. Oupu Volage Low (V OL) vs. T A Figure 18. Resar Timer Delay ( RST) vs. T A Figure 19. OVP Threshold a OVP Pin (V OVP,OVP) vs. T A Figure 20. Oupu Sauraion Volage (V RDY,SAT) vs. T A Figure 21. OVP Threshold Volage (V OVP) vs. T A FAN7930B Rev. 1.0.3 10
Applicaions Informaion 1. Sarup: Normally, supply volage (V CC) of a PFC block is fed from he addiional power supply, which can be called sandby power. Wihou his sandby power, auxiliary winding for zero curren deecion can be used as a supply source. Once he supply volage of he PFC block exceeds 12 V, inernal operaion is enabled unil he volage drops o 8.5 V. If V CC exceeds V Z, 20 ma curren is sinking from V CC. 2 nd OVP high disable 2. 885 OVP 2. 5 2.675 disable INV O pen 0. 35 0. 45 VIN PFC PFC Inducor VOUT PFC Aux. Winding 3 COMP 2. 885 V 2.675 V / 2. 5V 0.45 V / 0.35 V OVP 2 VOUT PFC 2.5V INV 1 Exernal V CC circui when no sandby power exiss. Figure 23. Circui Around INV Pin V PFC OUT 390 V DC 413 V 390 V VREF VBIAS 2.5VREF inernal bias VCC H:open rese VZ VTH(S/S) 20mA V CC 8 70 V 55 V Figure 22. 8.5 12 Sarup Circui V INV 2.50 V 0. 45 V 2. 65V 2. 50 V 2.24 V 1. 64 V 0. 35 V V CC 2. INV Block: Scaleddown volage from he oupu is he inpu for he INV pin. Many funcions are embedded based on he INV pin: ransconducance amplifier, oupu OVP comparaor, and disable comparaor. For he oupu volage conrol, a ransconducance amplifier is used insead of he convenional volage amplifier. The ransconducance amplifier (volageconrolled curren source) aids he implemenaion of he OVP and disable funcions. The oupu curren of he amplifier changes according o he volage difference of he invering and noninvering inpu of he amplifier. To cancel down he line inpu volage effec on power facor correcion, he effecive conrol response of he PFC block should be slower han he line frequency and his conflics wih he ransien response of he conroller. Twopole onezero ype compensaion can mee boh requiremens. The OVP comparaor shus down he oupu drive block when he volage of he INV pin is higher han 2.675 V and here is 0.175 V hyseresis. The disable comparaor disables operaion when he volage of he invering inpu is lower han 0.35 V and here is 100 mv hyseresis. An exernal smallsignal MOSFET can be used o disable he IC, as shown in Figure 23. The IC operaing curren decreases o reduce power consumpion if he IC is disabled. Figure 24 is he iming char of he inernal circui near he INV pin when raed PFC oupu volage is 390 V DC and V CC supply volage is 15 V. 2. 0V I OUT COMP Disable OVP 15 V Curren Sourcing V CC < 2V, inernal logic is no alive. Inernal signals are unknown. Figure 24. I sinking Curren Sourcing Timing Char for INV Block 3. OVP Pin: OverVolage Proecion (OVP) is embedded by he informaion a he INV pin. Tha informaion comes from he oupu hrough he volage dividing resisors. To scale down from a high volage o a low one, high resisance is normally used wih low resisance. If he resisor of high resisance ges damaged and resisance is changed o high, hough INV pin informaion is normal, oupu volage exceeds is raed oupu. If his occurs, he oupu elecrolyic capacior may be damaged. To preven such a caasrophe addiional OVP pin is assigned o doublecheck oupu volage. Addiional OVP may be called second OVP, while INV pin OVP is called firs OVP. Since he wo OVP condiions are quie differen, he proecion recovering mode is differen. FAN7930B Rev. 1.0.3 11
Since he wo OVP condiions are quie differen, proecion recovering mode is differen. Once he firs OVP riggers, swiching sops immediaely and recovers swiching when he oupu volage is decreased wih a hyseresis. When he second OVP riggers, swiching can be recovered only when he V CC supply volage falls below V STOP and builds up higher han V START again and V OVP should be lower han hyseresis. If he second OVP is no used, he OVP pin mus be conneced o he INV pin or o he ground. VCC VSTOP VSTART where V AUX is he auxiliary winding volage; T IND and T AUX are boos inducor urns and auxiliary winding urns, respecively; V AC is inpu volage for PFC converer; and V OUT_PFC is oupu volage from he PFC converer. RZCD VIN PFC ZCD 5 PFC Inducor Aux. Winding VCC Negaive Clamp Circui VOUT PFC VINV INV OVP Level hyseresis Error on INV Resisors Happens CZCD Opional Posiive Clamp Circui THD Opimized Sawooh Generaor VTH(ZCD) S R Resar Timer Q Q fmax Limi Gae Driver VOVP IMOSFET Swiching sop only during OVP Figure 25. OVP Level Though Oupu Volage Reduced, no Swiching. Swiching sop unil VCC drops below VSTOP and recovers o VSTART OVP Level If error sill exis, OVP riggers again Comparison of Firs and Second OVP Recovery Modes 4. Conrol Range Compensaion: On ime is conrolled by he oupu volage compensaor wih FAN7930B. Due o his when inpu volage is high and load is ligh, conrol range becomes narrow compared o when inpu volage is low. Tha conrol range decrease is inversely proporional o he double square of he inpu volage ( conrol range 1 inpu volage 2 ). Thus a high line, unwaned burs operaion easily happens a ligh load and audible noise may be generaed from he boos inducor or inducor a inpu filer. Differen from he oher converers, burs operaion in PFC block is no needed because he PFC block iself is normally disabled during sandby mode. To reduce unwaned burs operaion a ligh load, an inernal conrol range compensaion funcion is implemened and shows no burs operaion unil 5% load a high line. 5. ZeroCurren Deecion: Zerocurren deecion (ZCD) generaes he urnon signal of he MOSFET when he boos inducor curren reaches zero using an auxiliary winding coupled wih he inducor. When he power swich urns on, negaive volage is induced a he auxiliary winding due o he opposie winding direcion (see Equaion 1). Posiive volage is induced (see Equaion 2) when he power swich urns off: T V AUX AUX VAC TIND T V AUX AUX VPFCOUT VAC TIND (1) (2) Figure 26. Circui Near ZCD Because auxiliary winding volage can swing from negaive o posiive volage, he inernal block in ZCD pin has boh posiive and negaive volage clamping circuis. When he auxiliary volage is negaive, an inernal circui clamps he negaive volage a he ZCD pin around 0.65 V by sourcing curren o he serial resisor beween he ZCD pin and he auxiliary winding. When he auxiliary volage is higher han 6.5 V, curren is sinked hrough a resisor from he auxiliary winding o he ZCD pin. ISW IMOSFET VAUX & VZCD VAUX IDIODE VZCD VACIN 6.2V 0.65V Figure 27. Auxiliary Volage Depends on MOSFET Swiching The auxiliary winding volage is used o check he boos inducor curren zero insance. When boos inducor curren becomes zero, here is a resonance beween boos inducor and all capaciors a he MOSFET drain pin, including C OSS of he MOSFET; an exernal capacior a he DS pin o reduce he volage rising and falling slope of he MOSFET; a parasiic capacior a inducor; and so on o improve performance. Resonaed volage is refleced o he auxiliary winding and can be used for deecing zero curren of boos inducor and valley posiion of MOSFET volage sress. For valley deecion, a minor delay by he resisor and capacior is needed. A capacior increases he noise immuniy a he ZCD pin. If ZCD volage is higher han 1.5 V, an inernal ZCD comparaor oupu becomes HIGH and LOW when he ZCD goes below 1.4 V. A he falling edge of comparaor oupu, inernal logic urns on he MOSFET. FAN7930B Rev. 1.0.3 12
V DS This slighly degrades he power facor performance a ligh load and high inpu volage. V OUT PFC V IN ZCD afer COMPARATOR Ignores ZCD Noise V OUT PFC V IN V IN I INDUCTOR MOSFET Gae Error Occurs! Max fsw Limi I MOSFET I DIODE V ZCD Figure 30. Inhibi Region Maximum Swiching Frequency Limi Operaion MOSFET gae ON 1.5V 1.4V 150ns Delay ON 6. Conrol: The scaled oupu is compared wih he inernal reference volage and sinking or sourcing curren is generaed from he COMP pin by he ransconducance amplifier. The error amplifier oupu is compared wih he inernal sawooh waveform o give proper urnon ime based on he conroller. V OUT PFC Figure 28. Auxiliary Volage Threshold When no ZCD signal is available, he PFC conroller canno urn on he MOSFET, so he conroller checks every swiching off ime and forces MOSFET urn on when he off ime is longer han 150 μs. This resar imer riggers MOSFET urnon a sarup and may be used a he inpu volage zero cross period. V OUT V IN C2 INV COMP R1 C1 1 3 6.2V THD opimized 1V Sawooh Generaor Sawooh MOSFET Off VREF Sair Sep Clamp Circui V CC RESTART 150 s MOSFET G ae ZCD afer COMPARATOR Figure 29. Resar Timer a Sarup Because he MOSFET urnon depends on he ZCD inpu, swiching frequency may increase o higher han several megaherz due o he misriggering or noise on he nearby ZCD pin. If he swiching frequency is higher han needed for criical conducion mode (CRM), operaion mode shifs o coninuous conducion mode (CCM). In CCM, unlike CRM where he boos inducor curren is rese o zero a he nex swich on; inducor curren builds up a every swiching cycle and can be raised o very high curren ha exceeds he curren raing of he power swich or diode. This can seriously damage he power swich. To avoid his, maximum swiching frequency limiaion is embedded. If ZCD signal is applied again wihin 3.3 μs afer he previous rising edge of gae signal, his signal is ignored inernally and FAN7930B wais for anoher ZCD signal. Figure 31. Conrol Circui Unlike a convenional volagemode PWM conroller, FAN7930B urns on he MOSFET a he falling edge of ZCD signal. The ON insan is deermined by he exernal signal and he urnon ime lass unil he error amplifier oupu (V COMP) and sawooh waveform mee. When load is heavy, oupu volage decreases, scaled oupu decreases, COMP volage increases o compensae low oupu, urnon ime lenghens o give more inducor urnon ime, and increased inducor curren raises he oupu volage. This is how a PFC negaive feedback conroller regulaes oupu. The maximum of V COMP is limied o 6.5 V, which dicaes he maximum urnon ime. Swiching sops when V COMP is lower han 1.0 V. ZCD afer COMPARATOR VCOMP & Sawooh MOSFET Gae Figure 32. 0.155 V / s TurnOn Time Deerminaion FAN7930B Rev. 1.0.3 13
The roles of PFC conroller are regulaing oupu volage and inpu curren shaping o increase power facor. Duy conrol based on he oupu volage should be fas enough o compensae oupu volage dip or overshoo. For he power facor, however, he conrol loop mus no reac o he flucuaing AC inpu volage. These wo requiremens conflic; herefore, when designing a feedback loop, he feedback loop should be leas en imes slower han AC line frequency. Tha slow response is made by C1 a he compensaor. R1 makes gain boos around operaion region and C2 aenuaes gain a higher frequency. Boos gain by R1 helps raise he response ime and improves phase margin. VCC VSTART=12V VREF SS gm 5ms VINV=0.4V VREF END =2.5V Gain C 1 Inegraor Proporional Gain ISOURCE COMP (VREF SS VINV) gm=isource COMP R 1 Freq. VCOMP ISOURCE COMP RCOMP=VCOMP C 2 Figure 33. HighFrequency Noise Filer Compensaors Gain Curve For he ransconducance error amplifier side, gain changes based on differenial inpu. When he error is large, gain is large o suppress he oupu dip or peak quickly. When he error is small, low gain is used o improve power facor performance. I COMP Sourcing Sinking Powering 250 mho 2.4V 115 mho Figure 34. 2.5V 2.6V Braking Gain Characerisic Figure 35. SofSar Sequence 8. Sarup wihou Overshoo: Feedback conrol speed of PFC is quie slow. Due o he slow response, here is a gap beween oupu volage and feedback conrol. Tha is why overvolage proecion (OVP) is criical a he PFC conroller and volage dip caused by fas load changes from ligh o heavy is diminished by a bulk capacior. OVP can be riggered during sarup phase. Operaion on and off by OVP a sarup may cause audible noise and can increase volage sress a sarup, which is normally higher han in normal operaion. This operaion is improved when sofsar ime is very long. However, oo much sarup ime enlarges he oupu volage building ime a ligh load. FAN7930B has overshoo proecion a sarup. During sarup, he feedback loop is conrolled by an inernal proporional gain conroller and when he oupu volage reaches he raed value, i swiches o an exernal compensaor afer a ransiion ime of 30 ms. This inernal proporional gain conroller eliminaes overshoo a sarup and an exernal convenional compensaor akes over successfully aferward. VOUT Sarup Overshoo Convenional Conroller 7. SofSar: When V CC reaches V START, he inernal reference volage is increased like a sair sep for 5 ms. As a resul, V COMP is also raised gradually and MOSFET urnon ime increases smoohly. This reduces volage and curren sress on he power swich during sarup. VCOMP Overshooless Sarup Conrol Conrol Transiion Depend on Load Inernal Conroller Figure 36. Sarup wihou Overshoo FAN7930B Rev. 1.0.3 14
9. THD Opimizaion: Toal harmonic disorion (THD) is he facor ha dicaes how closely inpu curren shape maches sinusoidal form. The urnon ime of he PFC conroller is almos consan over one AC line period due o he exremely low feedback conrol response. The urnoff ime is deermined by he curren decrease slope of he boos inducor made by he inpu volage and oupu volage. Once inducor curren becomes zero, resonance beween C OSS and he boos inducor makes oscillaing waveforms a he drain pin and auxiliary winding. By checking he auxiliary winding volage hrough he ZCD pin, he conroller can check he zero curren of boos inducor. A he same ime, a minor delay is insered o deermine he valley posiion of drain volage. The inpu and oupu volage difference is a is maximum a he zero cross poin of AC inpu volage. The curren decrease slope is seep near he zero cross region and more negaive inducor curren flows during a drain volage valley deecion ime. Such a negaive inducor curren cancels down he posiive curren flows and inpu curren becomes zero, called zerocross disorion in PFC. I IN To improve his, lenghened urnon ime near he zero cross region is a wellknown echnique, hough he mehod may vary and may be proprieary. FAN7930B opimizes his by sourcing curren hrough he ZCD pin. Auxiliary winding volage becomes negaive when he MOSFET urns on and is proporional o inpu volage. The negaive clamping circui of ZCD oupus he curren o mainain he ZCD volage a a fixed value. The sourcing curren from he ZCD is direcly proporional o he inpu volage. Some porion of his curren is applied o he inernal sawooh generaor ogeher wih a fixedcurren source. Theoreically he fixedcurren source and he capacior a sawooh generaor deermine he maximum urnon ime when no curren is sourcing a ZCD clamp circui and available urnon ime ges shorer proporional o he ZCD sourcing curren. R ZCD V AUX THD Opimizer VCC N 1 I INDUCTOR IMOSFET IDIODE ZCD 5 V ZCD INEGATIVE Zero Curren Deec 1.5V VREF 1.4V IMOT MOSFET Gae 150ns rese CMOT ON ON Sawooh Generaor Figure 37. Inpu and Oupu Curren Near Inpu Volage Peak I IN V ZCD ON Figure 39. Circui of THD Opimizer ON is ypically consan over 1 AC line frequency bu ON is changed by ZCD volage. I INDUCTOR V ZCD INEGATIVE ON no shorer ON ge shorer 1.5V V ZCD a FET on 1.4V 150ns MOSFET Gae ON ON ON ON Figure 38. Inpu and Oupu Curren Near Inpu Volage Peak Zero Cross Figure 40. Effec of THD Opimizer By THD opimizer, urnon ime over one AC line period is proporionally changed, depending on inpu volage. Near zero cross, lenghened urnon ime improves THD performance. FAN7930B Rev. 1.0.3 15
10. V INAbsen Deecion: To reduce power loss caused by inpu volage sensing resisors and o opimize THD, he FAN7930B omis AC inpu volage deecion. Therefore, no informaion abou AC inpu is available from he inernal conroller. In many cases, he V CC of PFC conroller is supplied by an independen power source like sandby power. In his scheme, some mismach may exis. For example, when he elecric power is suddenly inerruped during wo or hree AC line periods; V CC is sill live during ha ime, bu oupu volage drops because here is no inpu power source. Consequenly, he conrol loop ries o compensae for he oupu volage drop and V COMP reaches is maximum. This lass unil AC inpu volage is live again. When AC inpu volage is live again, high V COMP allows high swiching curren and more sress is pu on he MOSFET and diode. To proec agains his, FAN7930B checks if he inpu AC volage exiss. If inpu does no exis, sofsar is rese and wais unil AC inpu is live again. Sofsar manages he urnon ime for smooh operaion when i deecs AC inpu is applied again and applies less volage and curren sress on sarup. V OUT V IN V AUX MOSFET Gae NewV COMP Though V IN is eliminaed, operaion of conroller is normal due o he large bypass capacior. D MAX f MIN f MIN D MIN Inpu Volage Absen Deeced V OUT V IN I DS Smooh Sof Sar V AUX Though V IN is eliminaed, operaion of conroller is normal due o he large bypass capacior. Figure 42. Wih V INAbsen Circui 11. Curren Sense: The MOSFET curren is sensed using an exernal sensing resisor for overcurren proecion. If he CS pin volage is higher han 0.8 V, he overcurren proecion comparaor generaes a proecion signal. An inernal RC filer of 40 kω and 8 pf is included o filer swiching noise. MOSFET Gae V COMP f MIN D MAX 12. Gae Driver Oupu: FAN7930B conains a single oempole oupu sage designed for a direc drive of he power MOSFET. The drive oupu is capable of up o 500 / 800 ma peak curren wih a ypical rise and fall ime of 50 ns wih 1 nf load. The oupu volage is clamped o 13 V o proec he MOSFET gae even if he V CC volage is higher han 13 V. I DS High Drain Curren! Figure 41. Wihou V INAbsen Circui FAN7930B Rev. 1.0.3 16
PCB Layou Guide PFC block normally handles high swiching curren and he volage lowenergy signal pah can be affeced by he highenergy pah. Cauious PCB layou is mandaory for sable operaion. The gae drive pah should be as shor as possible. The closedloop ha sars from he gae driver, MOSFET gae, and MOSFET source o ground of PFC conroller should be as close as possible. This is also crossing poin beween power ground and signal ground. Power ground pah from he bridge diode o he oupu bulk capacior should be shor and wide. The sharing posiion beween power ground and signal ground should be only a one posiion o avoid ground loop noise. Signal pah of he PFC conroller should be shor and wide for exernal componens o conac. The PFC oupu volage sensing resisor is normally high o reduce curren consumpion. This pah can be affeced by exernal noise. To reduce noise poenial a he INV pin, a shorer pah for oupu sensing is recommended. If a shorer pah is no possible, place some dividing resisors beween PFC oupu and he INV pin closer o he INV pin is beer. Relaive high volage close o he INV pin can be helpful. The ZCD pah is recommended close o auxiliary winding from boos inducor and o he ZCD pin. If ha is difficul, place a small capacior (below 50 pf) o reduce noise. The swiching curren sense pah should no share wih anoher pah o avoid inerference. Some addiional componens may be needed o reduce he noise level applied o he CS pin. A sabilizing capacior for V CC is recommended as close as possible o he V CC and ground pins. If i is difficul, place he SMD capacior as close o he corresponding pins as possible. Figure 43. Recommended PCB Layou FAN7930B Rev. 1.0.3 17
Typical Applicaion Circui Applicaion Device Inpu Volage Range Raed Oupu Power Oupu Volage (Maximum Curren) LCD TV Power Supply FAN7930B 90265 V AC 195 W 390 V (0.5 A) Feaures Average efficiency of 25%, 50%, 75%, and 100% load condiions is higher han 95% a universal inpu. Power facor a raed load is higher han 0.98 a universal inpu. Toal Harmonic Disorion (THD) a raed load is lower han 15% a universal inpu. Key Design Noes When auxiliary V CC supply is no available, V CC power can be supplied hrough Zero Curren Deec (ZCD) winding. The power consumpion of R103 is quie high, so is power raing needs checking. Because he inpu bias curren of INV pin is almos zero, oupu volage sensing resisors (R112~R115) should be as high as possible. However, oohigh resisance makes he node suscepible o noise. Resisor values need o srike a balance beween power consumpion and noise immuniy. Quick charge diode (D106) can be eliminaed if oupu diode inrush curren capabiliy is sufficien. Even wihou D106, sysem operaion is normal due o he conroller s highly reliable proecion feaures. Schemaic Opional D106 600V 3A 194 H, 39:5 D105 600V 8A DC OUTPUT BD101, 600V,15A C102, 680nF C114, 2.2nF C115, 2.2nF TH101, 5D15 LF101, 23mH C1030,68 F,630Vdc R102, 330k C107, 33 F C105, 100nF R104, 30k D101,1N4746 R107, C108, 10k 220nF R103, 10k,1W C104, 12nF C109, 47nF 6 VAUX D102, UF4004 FAN7930B 8 7 VCC Ou 5 ZCD 4 CS 3 Comp 2 INV 1 OVP GND R110,10k LP101,EER3019N R108 4.7 R109 47 D103,1N4148 D104,1N4148 C112,470pF Q101 FCPF 20N60 R111 0.08, 5W C110,1nF R112 3.9M R113 3.9M R114 3.9M R115 75k C116,1nF R116 3.9M R117 3.9M R118 3.9M R119 75k C111 220 F, 450V C101, 220nF R101,1MJ FS101, 250V,5A ZNR101, 10D471 Circui for VCC. If exernal VCC is used, his circui is no needed. Figure 44. Demonsraion Circui FAN7930B Rev. 1.0.3 18
Transformer 9,10 EER3019N 1,2 Naux 9,10 6,7 Naux N P 1,2 6,7 3,4 N p 3,4 Figure 45. Transformer Schemaic Diagram Winding Specificaion Posiion No Pin (S F) Wire Turns Winding Mehod Boom Top N p 3, 4 1, 2 0.1φ 50 39 Solenoid Winding Insulaion: Polyeser Tape = 0.05mm, 3 Layers N AUX 9,10 6,7 0.3φ 5 Solenoid Winding Insulaion: Polyeser Tape = 0.05 mm, 4 Layers Elecrical Characerisics Pin Specificaion Remark Inducance 3, 4 1, 2 194 H ±5% 100 khz, 1 V Core & Bobbin Core: EER3019, Samhwa (PL7) (Ae=137.0mm 2 ) Bobbin: EER3019 FAN7930B Rev. 1.0.3 19
Bill of Maerials Par # Value Noe Par # Value Noe Resisor Swich R101 1 MW 1W Q101 FCPF20N60 20 A, 600 V, SuperFET R102 330 kw 1/2W Diode R103 10 kw 1W D101 1N4746 1 W, 18 V, Zener Diode R104 30 kw 1/4W D102 UF4004 1 A, 400 V Glass Passivaed HighEfficiency Recifier R107 10 kw 1/4W D103 1N4148 1 A, 100 V SmallSignal Diode R108 4.7 kw 1/4W D104 1N4148 1 A, 100 V SmallSignal Diode R109 47 kw 1/4W D105 R110 10 kw 1/4W D106 R111 0.80 kw 5W R112, R113, R114, R116, R117, R118 8 A, 600 V, GeneralPurpose Recifier 3 A, 600 V, GeneralPurpose Recifier 3.9 kw 1/4W IC101 FAN7930B CRM PFC Conroller R115, R119 75 kw 1/4W Capacior C101 220 nf / 275 V AC Box Capacior FS101 5 A / 250 V Fuse C102 680 nf / 275 V AC Box Capacior NTC C103 0.68 µf / 630 V Box Capacior TH101 5D15 C104 12 nf / 50 V Ceramic Capacior Bridge Diode C105 100 nf / 50 V SMD (1206) BD101 15 A, 600 V C107 33 µf / 50 V Elecrolyic Capacior Line Filer C108 220 nf / 50 V Ceramic Capacior LF101 23 mh C109 47 nf / 50 V Ceramic Capacior Transformer C110, C116 1 nf / 50 V Ceramic Capacior T1 EER3019 Ae=137.0mm 2 C112 47 nf / 50 V Ceramic Capacior ZNR C111 220 µf / 450 V Elecrolyic Capacior ZNR101 10D471 C114 2.2 nf / 450 V Box Capacior C115 2.2 nf / 450 V Box Capacior FAN7930B Rev. 1.0.3 20
Physical Dimensions 8 5.00 4.80 3.81 5 A B 0.65 6.20 5.80 4.00 3.80 1.75 5.60 PIN ONE INDICATOR 8 0 (0.33) 1.75 MAX R0.10 0.90 0.40 R0.10 1 0.25 0.10 DETAIL A SCALE: 2:1 4 0.51 0.33 1.27 0.50 0.25 (1.04) 0.25 C B A C x 45 GAGE PLANE 0.36 SEATING PLANE 0.10 LAND PATTERN RECOMMENDATION SEE DETAIL A OPTION A BEVEL EDGE 1.27 OPTION B NO BEVEL EDGE 0.25 0.19 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X1758M. E) DRAWING FILENAME: M08Arev14 F) FAIRCHILD SEMICONDUCTOR. Figure 46. 8Lead, Small Ouline Package (SOP) Package drawings are provided as a service o cusomers considering Fairchild componens. Drawings may change in any manner wihou noice. Please noe he revision and/or dae on he drawing and conac a Fairchild Semiconducor represenaive o verify or obain he mos recen revision. Package specificaions do no expand he erms of Fairchild s worldwide erms and condiions, specifically he warrany herein, which covers Fairchild producs. Always visi Fairchild Semiconducor s online packaging area for he mos recen package drawings: hp://www.fairchildsemi.com/dwg/m0/m08a.pdf. FAN7930B Rev. 1.0.3 21
FAN7930B Rev. 1.0.3 22 FAN7930B Criical Conducion Mode PFC Conroller
Mouser Elecronics Auhorized Disribuor Click o View Pricing, Invenory, Delivery & Lifecycle Informaion: Fairchild Semiconducor: FAN7930BMX_G