Low Power VLSI Circuit Synthesis: Introduction and Course Outline Ajit Pal Professor Department of Computer Science and Engineering Indian Institute of Technology Kharagpur INDIA -721302
Agenda Why Low Power? Low Power Design methodology Course Outline
Why Low-power? Until recently performance has been synonymous with circuit speed or processing power, e.g. MIPS or MFLOPS. Implementation involved Area-Time tradeoff. Power Consumption = k.a.f, where k= 0.063 W/cm 2.MHz, A is the area in cm 2 and f is the frequency in MHz. Power consumption were of secondary concern.
Why Low-power? Contemporary high performance processors consume heavy power Cost associated with packaging and cooling such devices is prohibitive Low-power methodology to be used to reduce cost of packaging and cooling Clock Technology V dd Peak Power Processor (MHz) (mm) (Volt) (Watt) Ultra Sparc 167 0.45 3.3 30 Intel Pentium 200 0.50 3.3 26 Alpha 21064 200 0.50 3.3 30 Alpha 21164 300 0.45 3.3 50 Alpha 21264 667 0.35 2.0 72 Alpha 21364 1000 0.25 1.5 100
Processor Power
Why Low-power?
Why Low-power? Emergence of portable computing and communication equipment, such as laptops, palmtops, cell-phones, etc. Growth rate of these portable equipment are very high. As these devices are battery operated, battery life is of primary concern. Unfortunately, the battery technology has not kept up with the energy requirement of the portable equipment. Commercial success of these products depend on weight, cost and battery life. Low power design methodology is very important to make them commercially viable.
Why Low-power? Reliability is closely related to power dissipation Every 10ºC rise in temperature roughly doubles the failure rate Thermal runway Gate dielectric Junction diffusion Electromigration diffusion Electrical parameter shift Package related failure Silicon interconnect fatigue 0 100 200 300 o C above normal operating temperature Onset temperatures of various failure mechanism
Why Low-power? According to an estimate of the U.S. Environmental Protection Agency (EPA), 80% of the power consumption by office equipment are due to computing equipment and a large part from unused equipment Power is dissipated mostly in the form of heat. The cooling techniques, such as AC transfer the heat to the environment. To reduce adverse effect on environment efforts such as EPA s Energy Star program leading to power management standard for desktops and laptops has emerged. Drive towards Green PC
Low-Power Design Methodology Low-power design methodologies are to be applied throughout the design process from system-level to layout-level, gradually refining or detailing the abstract specification or model of the design. Starting with the system specification the following steps are performed to get the layout: System Specification =>System-level Design Behavioral Description => High-level Synthesis Structural RTL Description => Logic Synthesis Logic-level netlist => Layout Synthesis => Layout
Example: Bar Code Scanner System specification BARCODE SCANNER Mem_write Scan Camera addr Pre-processor Video Start eoc data Memory SYSTEM-LEVEL DESIGN HW/SW allocation/partitioning Selection of processor(s) Communication mechanism Microprocessor Addr Data Mem_read ARCHITECTURE algorithm OF barcode IS Pre_proc:PROCESS BEGIN...... LOOP IF video = wh THEN white := white + 1; IF falg = bl THEN...... flag = wh; black := 0; data <= white; ELSE black := black + 1;..... flag := bl; white := 0; data <= black; END IF; addr <= actnum; EXIT WHEN (white = limit) OR (black = limit) END LOOP;...... END algorithm; Behavioral description HIGH-LEVEL SYNTHESIS Transformations Scheduling Module selection Clock selection Resource sharing RTL optimizations Structural RTL description
Example: Bar Code Scanner flag m 6 wh bl zero white zero black limit limit 0 1 m 2 0 1 m 1 0 1 = = = Next Stage Logic Decode Logic m 1 m 24 zero black white zero m 13 0 1 m 12 0 1 white m 21 0 1 m 14 0 1 data m 22 0 1 white incre2 Structural RTL description LOGIC-SYNTHESIS Two-level, multi-level synthesis State assignment Retiming Technology mapping Logic level netlist LAYOUT-SYNTHESIS Placement. Routing Gate and wire sizing Clock distribution Power supply distribution Layout
System-level Design At the system level, the design may be modeled as a set of abstract communicating processes or tasks The tasks may be implemented either in hardware or compiled into software running on an embedded processor System-level synthesis involved partitioning the tasks into hardware and software, choosing the processors that will execute the software, determining the hardware/software communication mechanism, etc. This step will involve hardware/software tradeoff. Example: Use of VLIW Architecture instead of Superscalar Architecture The software component go through the software implementation steps, not to be covered in this course Dynamic voltage scaling
Architecture-level Synthesis The hardware part to be implemented is represented by behavioral or algorithmic descriptions High-level synthesis converts a behavioral description into a structural RTL implementation, which is represented as an interconnection of macroblocks and random logic. This step involves scheduling of operations to different cycles of execution and allocation to the available hardware resources. Low-power design methodologies, such as power management, parallelism, pipelining, reduction of the number of global busses, etc can be adopted. Techniques like loop unrolling, loop folding are used to reduce energy requirements
Logic Synthesis The macroblocks can be directly fed to the logic synthesis step, where as the random logic part is converted into logic-level netlist by the logic synthesis phase in two steps. The first step transforms into technologyindependent logic-level netlist, which is mapped into a semi-custom technology library. At this level, low-power techniques, such as reduction of switching activity, use of suitable logic family, use of multiple power supply, use of multiple threshold voltages, use of encoding for sequential circuits, clock gating, etc are used.
Layout Synthesis Layout synthesis is also carried out in a hierarchical framework, each stage is optimized, while making the problem manageable to the subsequent steps. Typically the following substages are involved: Partitioning: It divides a circuit in smaller steps Flooreplanning: It determines the approximate location of each module in a rectangular chip area Placement: It determines the best position of each module Routing: To provide interconnections among various modules. It is usually done in two steps; global routing followed by detailed routing
Course Outline: Background Material 1. Basics of MOS Transistors (3): Fabrication steps of a MOS Transistor Structure of MOS Transistors The Fluid Model MOS Capacitor model MOS Transistor model Electrical Characteristics of MOS transistors Threshold Voltage Body Effect Channel Length Modulation Transistor Transconductance nmos Transistor as a switch pmos Transistor as a switch Transmission gate Transmission gate driving a large capacitive load Transmission gate driving a small capacitive load
Course Outline: Background Material 2. MOS Inverters (5): Generic MOS inverter Transfer Characteristics Noise margin Passive resistor as pull-up device nmos depletion mode transistor as pull-up nmos enhancement mode transistor as pull-up pmos transistor as pull-up CMOS inverter Voltage-current characteristics Transfer Characteristics Noise margin of CMOS inverter Switching characteristics of CMOS inverter Driving Large Capacitive Loads Super buffers BiCMOS Inverter Buffer Sizing
Course Outline: Background Material 3. MOS Combinational Circuits (4) Pass transistor Logic Gate Logic CMOS Circuit Realization Switching characteristics CMOS complex logic gates MOS Dynamic Circuits Example Combinational circuits
Course Outline: Background Material 4. Sources of Power dissipation (2): Static Power Dissipation i. Diode Leakage Power ii. Subthreshold Leakage Power iii. Leakage power DSM circuits Dynamic Power Dissipation i. Short Circuit Power ii. Switching Power iii. Glitching Power Degrees of Freedom
Course Outline: Low-Power Techniques 5. Supply Voltage Scaling Approaches (5): Device feature size scaling Multi-Vdd Circuits Architectural level approaches: Parallelism, Pipelining Voltage scaling using high-level transformations Dynamic voltage scaling Power Management
Course Outline: Low-Power Techniques 6. Switched Capacitance Minimization Approaches (5): Hardware Software Tradeoff Bus Encoding Two s complement Vs Sign Magnitude Architectural optimization Techniques Clock Gating Possible Logic styles
Course Outline: Low-Power Techniques 7. Leakage Power minimization Approaches (4) : Realization of Multithreshold Circuits Variable-threshold-voltage CMOS (VTCMOS) approach Multi-threshold-voltage CMOS (MTCMOS) approach Dual-Vt assignment approach (DTCMOS) Transistor stacking 8. Special Topics: Adiabatic Switching Circuits (1) Battery-aware Synthesis (1) Variation Tolerant Design (1)
References Text/Reference Books: T1: Sung_Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata Mcgrag Hill T2: Neil H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2 nd Edition, Addison Wesley (Indian reprint). T3: A. Bellamour, and M. I. Elmasri, Low Power VLSI CMOS Circuit Design, Kluwer Academic Press, 1995 R1: Anantha P. Chandrakasan and Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995 R2: Christian Piguet (Ed.), Low-Power CMOS Circuits: Technology, Logic Design and CAD Tools, Tayler and Francis (CRC), 2006
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