A Robust Design of Low Voltage CMOS Rail to Rail OpAmp Architecture Chi-Hung LIN, Hongwu CHI, Changku HWANG ;, and Mohammed ISMAIL. Department of Electrical Engineering, The Ohio State University. Micrys, Inc., Columbus, OH, USA Email: linc@er4.eng.ohio-state.edu, and ismail@ee.eng.ohio-state.edu Abstract In this paper, a CMOS rail to rail OpAmp architecture is presented for low voltage (<3V) applications. The input stage is implemented using a recently reported universal approach to achieve constant transconductance, g m. Transconductance control circuit is also introduced to compensate for K p, K n mismatch of PMOS and NMOS dierential pairs in the input stage. The input stage is designed for operation in the strong inversion and has a rail to rail common mode input voltage range. An output stage with class AB control circuit is utilized to provide a minimum standby current for lower static power consumption. I. Introduction Recently, many commercial electronic systems, such as cellular phones and lap-top computers, are implemented to meet a requirement of handy and smaller dimensions. The power supply voltage is also reduced to the level of a portable system or a battery-powered system with lower power dissipation. As the supply voltage is reduced, modications of analog circuits to maintain high performance become more necessary and dicult than those on digital circuits. Specially, the range of all analog signals is no longer completely covered, while the power supply voltage is also reduced. So a "rail to rail" operation []-[8] is required in a low voltage analog circuit. A complementary dierential pairs can achieve rail-to-rail operation well, and is used in the design of low-voltage OpAmps []-[8]. The complementary pair must have a constant g m in order to achieve a constant unity gain frequency with low total harmonic distortion, particularly in noninverting OpAmp circuits. A universal constant g m approach method []-[4] has recently been proposed for this purpose. This approach
VDD Maximum Current Selecting Circuit Vin+ Vin- Vin- Transconductance Equalizer Circuit Vin+ Maximum Current Selecting Circuit Iout Output Stage Iout Vout Figure : The robust schematic of low voltage rail to rail OpAmp works well regardless of the operation regions (weak or strong inversion) and the types of the transistors (MOS, BiCMOS, or Bipolar). Maximum Current Selecting Circuit is used to track the maximum signal currents independent of the common mode input voltage range (see Fig..). It not only enables the transconductance of the input stage to be more steady and constant, but also keeps the circuit of OpAmp compact and easy to design. A Transconductance Equalizer Bias Circuit [5] will be used in this paper to circumvent the requirement ofk p =K n for the fabrication mismatch. The output stage with class AB control buer is used to subtract the currents, and amplify the dierential voltage. Finally, two stage single-ended OpAmp architecture and the simulation results will be presented. II. Complementary Input Dierential Pairs with Maximum Current Selecting Circuits. As mentioned in the previous section, a constant g m input stage is the design issue of the OpAmp. The transconductance, g m, is dominated by the tail current of a transistor. That is g m = di d =dv gs = p KI bias () where K = n;pc ox Wn;p Ln;p. n;p is the electron mobility, C ox is the gate oxide capacitance, and Wn;p Ln:p is the aspect ratio of the transistor. In the dierential pairs, the total instantaneous output currents, or the drain currents, can be expressed as []-[4]: I n;n = I nbias g mn v id () I p;p = I pbias g mp v id (3)
for NMOS dierential pairs, and PMOS dierential pairs. The currents, I pbais and I nbias, are tail currents of PMOS and NMOS pairs. v id is the dierential mode input voltage. To maintain the transconductance of p-channel and n-channel dierential pairs equally at full swing range of the common mode input voltage, we should have g mp = p K p I pbias = p K n I nbias = g mn = g m;max (4) This means that I pbias =I nbias =I bias;max should be selected from rail to rail, and K p =K n should be assumed as the required condition. Going through Maximum Current Selecting Circuits []-[4] shown in Fig., the drain current pairs, (I n, I p) or (I p, I n), of the dierential pairs are selected straight atany common mode input voltage swing (see Fig.). Therefore, the output currents of the input stage with Maximum Selecting Current Circuit, (I out, I out), are equal to the maximum currents of (I p,i n) and (I p,i n). Obviously, the signal current can be extracted and expressed as: i out = I out, I out = g m;max v id (5) Consequently, the relationship in eq.(4) guarantees that the transconductance of the input stage as desired is always kept at a constant value, g m;max, in the entire common mode input voltage range. VDD Mpp Mpp Vb Mnx Iin Iin Mm5 Mm4 Mm3 Mm Mm Iout Figure : Maximum Current Selecting Circuit 3
III. Transconductance Equalizer Bias Circuit Ma8 VDD 4 : : 4 Ma9 Ma Ipbias Ma 5/4Inbias Ma Ipbias/4 to PMOS pair Ma3 Ma4 to NMOS pair Ma7 Inbias/4 Inbias 4 : Ma6 : 4 Ma5 Figure 3: Transconductance Equalizer Bias Circuit Nevertheless, the universal approach requires K p =K n. The fabrication process of integrated circuits could result in K p, K n mismatch of the transistors, this mismatch always exists in fabricated circuit and hence the performance of OpAmp would not be as good as predicted. Recently [5], the process parameters variations, p, n, in the. m Orbit,. m VTI, etc., used by the MOSIS service are studied. The deviations of p, n in these processes are found to be almost 3 %. This deviation may result in large g m variation in low-voltage rail to rail OpAmps. Transconductance Equalizer Circuit [5] is employed to secure the constant transconductance even when K p 6= K n resulting in a robust low-voltage OpAmp design. Let us assume that the given ratio of the electron mobility, n, is.8 approximately. If the design is carried out with this assumed p ratio value, this ratio with about % deviation will be between. and 3.3. This deviation will cause the tranconductance to vary around %. Under the conditions of K p = K n, I pbias =I nbias, the total transconductance is kept a constant. A more general robust approach should be based on the following condition to achieve eq.(6), p Kp I pbias = p K n I nbias (6) and a Transconductance Equalizer Circuit is shown in Fig.3. The bias circuit is supplied by a constant bias current, 5=4I nbias. The main part of the bias circuit is made up by Ma, Ma, Ma3, 4
Ma4. Using KVL around the four transistors, we have V sg + V gs3 = V sg + V gs4 (7) Because of the square law characteristics and the two current mirrors, Ma5, Ma6, Ma8, Ma9 with a current ratio of 4:, and V gs = V t +q Id, eq.(7) can be expressed as: K p p InbiasK n = I pbiask p (8) where the pair of the transisitors, Ma, Ma(Ma3, Ma4), has the same threshold voltages, V tp (V tn ). Obviously, the equation means that g mn is equal to g mp. As K p is not equal to K n, the bias circuit provides two dierent bias currents, I nbias, I pbias, to two dierential pairs for achieving g mn(max) = g mp(max). According to the above equation, no matter how the ratio of K p, K n, is changed, g mn and g mp should be equal with the adjustment of the bias currents and regardless of the ratio values of K p, K n. Of course, the simple current mirrors (Ma5, Ma6, Ma7, Ma8, Ma9, Ma) may suer from channel length modulation, this nonideal eect limits the compensation capability of Transconductance Equalizer Circuit within a narrow range of bias currents and limited ratios of K p, K n. IV. The Overall Input Stage Design So far, the blueprint of the rail to rail robust OpAmp input stage has been constructed. The circuit of the input stage (see Fig.4) will be implemented in this section. The simulation results in Fig.5(a) show that the operations of the input stage with the dierent bias currents, 5A, A, 5A, have dierent constant g m. With K p 6=K n, this input stage is simulated in the bias current range from A to4a. Fig.5(b) indicates that the drain currents of the input dierential pairs with 5A, A, 5A bias currents compensate for the mismatch of p-channel and n-channel input dierential pairs. The simulated variation percentage of g m is between 4.6 % and 6.67 %. Of course, one of the main goals of this OpAmp design is how to reduce the variation of transconductance due to the mismatch of the p-channel and n-channel dierential pairs in fabrication process. Some simulations based on the assumption of the ratio variations of K p, K n are done and shown in Fig.7. The deviation relationship of bias currents and K p, K n is dened as: Inbias Ipbias = K p( x) K n ( x) (9) 5
VDD VDD Vb Ibias Vb Iout Vin+ Vin- Vin- Vin+ Iout Figure 4: The robust rail to rail constant g m input stage x 4 (a). x 5 (b).4. Ibias=5uA Ibias=uA Ibias=5uA Ibias=5uA.8 Ibias=uA gm (A/V).8.6 In,In,Ip,Ip (A).6 Ip, Ip Ibias=5uA In, In.4.4.. 3 Vcm (V) 3 Vcm (V) Figure 5: (a) The transconductance of the input stage with dierent bias currents, 5A, A, 5A and (b) The drain currents of the input stage with 5A, A, 5A bias currents compensate for the mismatch of p-channel and n-channel input dierential pairs. x the smallest variation cases) 4 x the largest variation cases) 4.8.8.6.6.4.4.. gmt(a/v) gmt(a/v).8.8.6.6.4. % deviation 5% deviation % deviation.4. % deviation 5% deviation % deviation 3 Vcm(V) 3 Vcm(V) Figure 6: The simulated (a) smallest and (b) largest g m variation cases of %,5%,%K p,k n deviation 6
x 4 (b) N55O x 4 (a) N7V.8 gmn gmp gmt.8 gmn gmp gmt.6.6.4.4 gmn gmp gmt(a/v)..8 gmn gmp gmt(a/v)..8.6.6.4.4.. 3 Vcm (V) 3 Vcm (V) Figure 7: Two dierent MOSIS m Model, (a) N55O, (b) N7V, are used to test the function of Transconductance Equalizer Circuit where x is a random number between % and 5 %_ The smallest and largest variation cases with %, 5 %, % K p, K n deviations are displayed in Fig. 6(a), (b). Obviously, the transconductance of the input stage is still expected to be a stable constant value. The range of the estimated g m variation percentage with 5 % K p, K n deviations is from 4.76 % to 5.4 % for the smallest variation case and from 5.9 % to 8 % for the largest variation case. The major g m variation (Fig.6(b)) is caused by the reason that the output currents (I p, I p) enter into the triode region around V cm =.5V(see Fig.5(b)). From the simulation of frequency response of the input stage, the dominant pole is located around MHz. Fig.7(a), (b) show that two other dierent MOSIS models (N55O, N7V) are used to test the function of Transconductance Equalizer Circuit, the results are similar to the mismatch estimation of K p, K n. V. A Two Stage Low-voltage OpAmp In order to obtain the information of total transconductance due to current subtraction (see eq.(5)) and obtain voltage amplication, an output stage for this purpose is necessary for this OpAmp. The output stage [8] is composed of cascode gain and class AB control circuits, which is power-ecient, and has a rail-to-rail output swing. The output currents, I out and I out, are respectively connected with the output stage. A complete two stage single-ended operational amplier is shown in Fig.8. The simulation is based on SPICE level two model with 3 Volt power supply. Neither M o nor M o is turned o, the output stage always works from rail to rail. The minimum standby currents 7
VDD VDD Ibias Vb Ibias3 Vb Vin+ Vin- Vin- Vin+ Vb Vb3 Ibias C C Vout Figure 8: A two stage single-ended operational amplier 3 (a) (b) Vin Vout 9 Vcm=.5V.5 8 Vcm=.5V Vcm=.5V 7 6 Vout (V).5 Gain (db) 5 4 3.5 3 Vin (V) 5 Frequency (Hz) Figure 9: (a) the input-output voltage characteristics of the unity gain conguration (b) open loop frequency response of the OpAmp help to increase the speed during the operation. The input-output voltage characteristics of the unity gain conguration is shown in Fig.9(a). The output voltage almost match with the input voltage except for a range of.6v within both upper and lower rails. The open loop frequency response of OpAmp is shown in Fig.9(b). Because of constant transconductance of the input stage, the low frequency open loop gain, A o, and the unity gain frequency, f U, are constant from rail to rail. The performance of OpAmp with I bias=5a and R L =k, C L =p is specied in Table. The DC input oset voltage is -.3 V. The swing range of the output voltage is between.6v and.95v without distortion. The low frequency open loop gain approaches 86 db. The unity gain 8
frequency is.4 MHz, and the phase margin is always larger than 76 degree. Table shows the total harmonic distortion (THD) with a khz sinusoidal input signal wave. The total harmonic distortion is less than.4 % while the amplitude of the input wave within.4v is applied to this OpAmp. The total harmonic distortion at khz indicates a very low distortion percentage which is.4755 %,.4833 %,.584 % for V cm =.5,.5,.5 V respectively. The low voltage CMOS rail to rail OpAmp is simulated by SPICE and APLAC [9]. The chip has been fabricated using m ORBIT process by MOSIS service. The total area of the OpAmp is 563 x 65 m. Table : The performance of OpAmp with I bias=5a and R L =k, C L =p parameter DC input oset voltage Common mode input voltage Output voltage swing Open loop gain Unity gain frequency Phase margin Slew rate " Slew rate # CMRR @ MHz Positive PSRR Negative PSRR Total power dissipation value -.39 V Vto3V.6 V to.95 V 86 db.46 MHz 76 o. V/s.33 V/s 79 db db 9 db.6 mw VI. Conclusion A robust low voltage rail to rail OpAmp has been presented. A novel universal constant g m approach and Transconductance Equalizer Circuit are used for this OpAmp design. This method fully strengthens the robustness and improves the performance of OpAmp. The power dissipation is also reduced in this architecture. Therefore, it really simplies the design procedure, and the operation eciency of CMOS low-voltage OpAmps. Reference [] J. H. Huijsing and D. Linbarger,"Low-voltage operatinal amplier with rail-to-rail input and output ranges,"ieee J Solid-State Circuits. Circuits,vol. SC-, pp.44-5, Dec.985. 9
Table : Total harmonic distortion of OpAmp as unity gain buer V in (V) THD ( % )..38..6.3.78.4.8.5.75.6.5.7.57.8.65.9.5..74..36..93.3.3.4.46.5.3777 [] C. Hwang, A. Motamed,and M. Ismail,"Universal constant-gm input-stage architecture for low-voltage op amps",ieee Trans. Circuits and Systems, vol. 4 Nov. 995. [3] "A Constant-Transconductance Input Stage and Integrated Circuit Implementation Thereof", with A. Motamed, C. Hwang and M. Ismail U.S. Patent, pending(no.8/54.9),led August 4, 995. [4] C. Hwang, A. Motamed, M. Ismail, "Theory and Design of Universal Low-Voltage OpAmps", Ch..3 in Emerging Technologies Designing Low Power Digital Systems, R. Cavin and W. Liu(Editors), ISCAS/96 Tutorial book, May 996. IEEE Catalog No. 96TH889. [5] S. Sakurei, M. Ismail, "Robust design of rail-to-rail CMOS operational ampliers for a low power supply voltage", IEEE JSSC, vol. 3, no., Feb 996. [6] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, L. Fonderi, R. F. Wassenaar, J. H. Huijsing,"CMOS low-voltage operatinal amplier with constant gm rail-to-rail input stage", in Proc. IEEE Int. Symp. Circuits Syst., 99. [7] J. H. Botma, R. J. Wiegerink, S. L. J. Gierkink, and R. F. Wassenaar,"Rail-to-rail constant gm input stage and class AB output stage for low-voltage CMOS op amps", Analog Integrated Circuits Signal Process., vol. 6, pp. -33,993. [8] R. Hogervorst, J. P. Tero, G. H. Eschauzier, and J. H. Huijsing, "A Compact Power-Ecient 3V CMOS Rail-to-Rail Input/Output Operational Amplier for VLSI Cell Libraries", IEEE J. Solid-State Circuits, pp.55-53, Dec. 994. [9] Helsinki Univ. of Technol., Circuit Theory Lab. and Nokia Res. Center, APLAC-An Object-Oriented Analog Circuit Simultor and Design Tool, 7.3 User's Manuel and Reference Manuel, Jan. 996.