200V N-Channel MOSFET November 2001 General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters, switch mode power supplies, DC-AC converters for uninterrupted power supply and motor control. Features 15.8A, 200V, R DS(on) = 0.085Ω @ = 10 V Low gate charge ( typical 95 nc) Low Crss ( typical 75 pf) Fast switching 100% avalanche tested Improved dv/dt capability D! G D S TO-220F IRFS Series G!! S Absolute Maximum Ratings T C = 25 C unless otherwise noted Symbol Parameter Units S Drain-Source Voltage 200 V I D Drain Current - Continuous (T C = 25 C) 15.8 A - Continuous (T C = 100 C) 10 A I DM Drain Current - Pulsed (Note 1) 63 A S Gate-Source Voltage ± 30 V E AS Single Pulsed Avalanche Energy (Note 2) 600 mj I AR Avalanche Current (Note 1) 15.8 A E AR Repetitive Avalanche Energy (Note 1) 5.0 mj dv/dt Peak Diode Recovery dv/dt (Note 3) 5.0 V/ns P D Power Dissipation (T C = 25 C) 50 W - Derate above 25 C 0.4 W/ C T J, T STG Operating and Storage Temperature Range -55 to +150 C T L Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 300 C Thermal Characteristics Symbol Parameter Typ Max Units R θjc Thermal Resistance, Junction-to-Case -- 2.51 C/W R θja Thermal Resistance, Junction-to-Ambient -- 62.5 C/W Rev. B, November 2001
Electrical Characteristics T C = 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BS Drain-Source Breakdown Voltage = 0 V, I D = 250 µa 200 -- -- V BS Breakdown Voltage Temperature / T J Coefficient I D = 250 µa, Referenced to 25 C -- 0.2 -- V/ C I DSS = 200 V, = 0 V -- -- 10 µa Zero Gate Voltage Drain Current = 160 V, T C = 125 C -- -- 100 µa I GSSF Gate-Body Leakage Current, Forward = 30 V, = 0 V -- -- 100 na I GSSR Gate-Body Leakage Current, Reverse = -30 V, = 0 V -- -- -100 na On Characteristics (th) Gate Threshold Voltage =, I D = 250 µa 2.0 -- 4.0 V R DS(on) Static Drain-Source On-Resistance = 10 V, I D = 7.9 A -- 0.071 0.085 Ω g FS Forward Transconductance = 40 V, I D = 7.9 A (Note 4) -- 19 -- S Dynamic Characteristics C iss Input Capacitance = 25 V, = 0 V, -- 2600 3400 pf C oss Output Capacitance f = 1.0 MHz -- 330 430 pf C rss Reverse Transfer Capacitance -- 75 100 pf Switching Characteristics t d(on) Turn-On Delay Time -- 30 70 ns V DD = 100 V, I D = 32 A, t r Turn-On Rise Time R G = 25 Ω -- 240 490 ns t d(off) Turn-Off Delay Time -- 295 600 ns t f Turn-Off Fall Time (Note 4, 5) -- 195 400 ns Q g Total Gate Charge = 160 V, I D = 32 A, -- 95 123 nc Q gs Gate-Source Charge = 10 V -- 13 -- nc Q gd Gate-Drain Charge (Note 4, 5) -- 43 -- nc Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current -- -- 15.8 A I SM Maximum Pulsed Drain-Source Diode Forward Current -- -- 63 A V SD Drain-Source Diode Forward Voltage = 0 V, I S = 15.8 A -- -- 1.5 V t rr Reverse Recovery Time = 0 V, I S = 32 A, -- 220 -- ns Q rr Reverse Recovery Charge di F / dt = 100 A/µs (Note 4) -- 1.89 -- µc Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 3.6mH, I AS = 15.8A, V DD = 50V, R G = 25 Ω, Starting T J = 25 C 3. I SD 32A, di/dt 300A/µs, V DD BS, Starting T J = 25 C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature Rev. B, November 2001
Typical Characteristics I D, Drain Current [A] 10 1 Top : 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V I D, Drain Current [A] 10 1 10 0 150 o C 25 o C -55 o C 1. 250μ s Pulse Test 2. T C = 25 1. = 40V 2. 250μ s Pulse Test 10 0 10-1 10 0 10 1, Drain-Source Voltage [V] 10-1 2 4 6 8 10, Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.4 R DS(ON) [Ω ], Drain-Source On-Resistance 0.3 0.2 0.1 = 10V = 20V Note : T J = 25 I DR, Reverse Drain Current [A] 10 1 150 25 1. = 0V 2. 250μ s Pulse Test 0.0 0 30 60 90 120 I D, Drain Current [A] 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 V SD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature Capacitance [pf] 8000 6000 4000 2000 C iss C oss C rss C iss = C gs + C gd (C ds = shorted) C oss = C ds + C gd C rss = C gd 1. = 0 V 2. f = 1 MHz, Gate-Source Voltage [V] 12 10 8 6 4 2 = 40V = 100V = 160V Note : I D = 32 A 0 10-1 10 0 10 1, Drain-Source Voltage [V] 0 0 20 40 60 80 100 Q G, Total Gate Charge [nc] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics Rev. B, November 2001
Typical Characteristics (Continued) 1.2 3.0 2.5 BS, (Normalized) Drain-Source Breakdown Voltage 1.1 1.0 0.9 1. = 0 V 2. I D = 250 μ A R DS(ON), (Normalized) Drain-Source On-Resistance 2.0 1.5 1.0 0.5 1. = 10 V 2. I D = 16 A 0.8-100 -50 0 50 100 150 200 T J, Junction Temperature [ o C] 0.0-100 -50 0 50 100 150 200 T J, Junction Temperature [ o C] Figure 7. Breakdown Voltage Variation vs Temperature Figure 8. On-Resistance Variation vs Temperature I D, Drain Current [A] 10 2 10 1 10 0 10-1 Operation in This Area is Limited by R DS(on) 1. T C = 25 o C 2. T J = 150 o C 3. Single Pulse 100 ms DC 100 µs 1 ms 10 ms I D, Drain Current [A] 16 12 8 4 10-2 10 0 10 1 10 2, Drain-Source Voltage [V] 0 25 50 75 100 125 150 T C, Case Temperature [ ] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs Case Temperature Z θ JC (t), Therm al Response 10 0 10-1 D=0.5 0.2 0.1 0.05 0.02 0.01 single pulse 1. Z θ JC (t) = 2.51 /W M ax. 2. D uty Factor, D=t 1 /t 2 3. T JM - T C = P DM * Z θ JC (t) P DM t 1 t 2 10-2 10-5 10-4 10-3 10-2 10-1 10 0 10 1 t 1, Square Wave Pulse Duration [sec] Figure 11. Transient Thermal Response Curve Rev. B, November 2001
Gate Charge Test Circuit & Waveform 12V 200nF 50KΩ 300nF Same Type as DUT 10V Q g Q gs Q gd 3mA DUT Charge Resistive Switching Test Circuit & Waveforms R L 90% R G V DD 10V DUT 10% t d(on) t r t d(off) tf t on t off Unclamped Inductive Switching Test Circuit & Waveforms L 1 E AS = ---- LI 2 2 AS BS -------------------- BS -V DD I D BS I AS R G V DD I D (t) 10V DUT V DD (t) t p t p Time Rev. B, November 2001
Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + _ I SD L Driver R G Same Type as DUT V DD dv/dt controlled by RG I SD controlled by pulse period ( Driver ) Gate Pulse Width D = -------------------------- Gate Pulse Period 10V I FM, Body Diode Forward Current I SD ( DUT ) di/dt I RM Body Diode Reverse Current ( DUT ) Body Diode Recovery dv/dt V SD V DD Body Diode Forward Voltage Drop Rev. B, November 2001
Package Dimensions TO-220F 3.30 ±0.10 10.16 ±0.20 ø3.18 ±0.10 2.54 ±0.20 (7.00) (0.70) 15.80 ±0.20 6.68 ±0.20 (1.00x45 ) 15.87 ±0.20 9.75 ±0.30 MAX1.47 0.80 ±0.10 (30 ) 0.35 ±0.10 #1 0.50 +0.10 0.05 2.76 ±0.20 2.54TYP [2.54 ±0.20] 2.54TYP [2.54 ±0.20] 9.40 ±0.20 4.70 ±0.20 Dimensions in Millimeters Rev. B, November 2001
TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E 2 CMOS EnSigna FACT FACT Quiet Series STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms FAST FASTr FRFET GlobalOptoisolator GTO HiSeC ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC OPTOPLANAR PACMAN POP Power247 PowerTrench QFET QS QT Optoelectronics Quiet Series SLIENT SWITCHER 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition SMART START STAR*POWER Stealth SuperSOT -3 SuperSOT -6 SuperSOT -8 SyncFET TruTranslation TinyLogic UHC UltraFET VCX Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4
Careers Sitema Go DATASHEETS, SAMPLES, BUY TECHNICAL INFORMATION APPLICATIONS DESIGN CENTER SUPPORT COMPANY INVESTORS MY FA Home >> Find products >> 200V N-Channel B-FET / Substitute of IRFS650A Related Links Request samples Contents General description Features Product status/pricing/packaging Order Samples Qualification Support Datasheet Download this datasheet How to order products Product Change Notices (PCNs) Support General description These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters, switch mode power supplies, DC-AC converters for uninterrupted power supply and motor control. e-mail this datasheet This page Print version Sales support Quality and reliability Design center back to top Features 15.8A, 200V, R DS(on) = 0.085Ω @ = 10 V Low gate charge (typical 95 nc) Low Crss (typical 75 pf) Fast switching 100% avalanche tested Improved dv/dt capability back to top Product status/pricing/packaging
Product Product status Pb-free Status Package type Leads Packing method Package Marking Convention** _FP001 Not recommended for new designs TO-220F 3 RAIL Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &4 (4-Digit Date Code) Line 2: IRFS Line 3: 650B Indicates product with Pb-free second-level interconnect. For more information click here. Package marking information for product is available. Click here for more information. back to top Qualification Support Click on a product for detailed qualification data Product _FP001 back to top 2007 Fairchild Semiconductor Products Design Center Support Company News Investors My Fairchild Contact Us Site Index Privacy Policy Site Terms & Conditions Standard Terms & Conditions o