HA-5 Data Sheet August FN97. MHz, Fast Settling Operational Amplifier The Intersil HA-5 is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. Bipolar construction coupled with dielectric isolation allows this truly differential device to deliver outstanding performance in circuits where closed loop gain is 1 or greater. Additionally, the HA-5 has a drive capability of ±1V into a 1kΩ load. Other desirable characteristics include low input voltage noise, low offset voltage, and fast settling time. A V/µs slew rate ensures high performance in video and pulse amplification circuits, while the MHz gainbandwidth product is ideally suited for wideband signal amplification. A settling time of 1ns also makes the HA-5 an excellent selection for high speed Data Acquisition Systems. Refer to Application Note AN51 and Application Note AN55 for more information on High Speed Op Amp applications. For a lower power version of this product, please see the HA-5 datasheet. Features Very High Slew Rate...................... V/µs Fast Settling Time.......................... 1ns Wide Gain Bandwidth (A V 1).............. MHz Power Bandwidth........................... MHz Low Offset Voltage........................... mv Input Voltage Noise....................... nv/ Hz Output Voltage Swing........................ ±1V Monolithic Bipolar Construction Applications Pulse and Video Amplifiers Wideband Amplifiers High Speed Sample-Hold Circuits Fast, Precise D/A Converters Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. HA1-5- -55 to 15 1 Ld CERDIP F1.3 Pinout HA-5 (CERDIP, PDIP) TOP VIEW HA1-5-5 to 75 1 Ld CERDIP F1.3 HA3-5-5 to 75 1 Ld PDIP E1.3 1 1 13 3 1 -IN +IN 5 + - 11 1 OUTPUT 9 7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1--INTERSIL or 31-7-713 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.. All Rights Reserved
HA-5 Absolute Maximum Ratings Voltage Between and Terminals.................... 35V Differential Input Voltage............................... V Output Current.............. 33mA RMS Continuous, 5mA PEAK Operating Conditions Temperature Range HA-5-.............................. -55 o C to 15 o C HA-5-5................................ o C to 75 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) CERDIP Package................. 75 PDIP Package................... 1 N/A Maximum Internal Power Dissipation (Note 1) Maximum Junction Temperature (Ceramic Package)...... 175 o C Maximum Junction Temperature (Plastic Package).........15 o C Maximum Storage Temperature Range.......... -5 o C to 15 o C Maximum Lead Temperature (Soldering 1s)............ 3 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175 o C for the ceramic package, and below 15 o C for the plastic package. By using Application Note AN55 on Safe Operating Area Equations, along with the thermal resistances, proper load conditions can be determined. Heat sinking is recommended above 75 o C.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±15V, R L = 1kΩ, C L < 1pF, Unless Otherwise Specified TEMP HA-5- HA-5-5 PARAMETER ( o C) MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 5-1 - 15 mv Full - 13 15-13 mv Average Offset Voltage Drift Full - - - - µv/ o C Bias Current 5-5 - 5 µa Full - - 5 - - 5 µa Offset Current 5-1 - 1 µa Full - - - - µa Input Resistance 5-1 - - 1 - kω Input Capacitance 5-1 - - 1 - pf Common Mode Range Full ±1 - - ±1 - - V Input Noise Current (f = 1kHz, R SOURCE = Ω) 5 - - - - pa/ Hz Input Noise Voltage (f = 1kHz, R SOURCE = Ω) 5 - - - - nv/ Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) 5 1 15-1 15 - kv/v Full 5 - - 5 - - kv/v Common-Mode Rejection Ratio (Note ) Full 7-7 - db Minimum Stable Gain 5 1 - - 1 - - V/V Gain Bandwidth Product (Notes 5, ) 5 - - - - MHz OUTPUT CHARACTERISTICS Output Voltage Swing (Notes 3, 1) Full ±1 - - ±1 - - V Output Current (Note 3) 5 ±1 ± - ±1 ± - ma Output Resistance 5-3 - - 3 - Ω Full Power Bandwidth (Notes 3, 7) 5 5.5-5.5 - MHz TRANSIENT RESPONSE (Note ) Rise Time 5-1 - - 1 - ns Overshoot 5-5 - - 5 - % Slew Rate 5 3-3 - V/µs Settling Time: 1V Step to.1% 5-1 - - 1 - ns POWER REQUIREMENTS Supply Current Full - 5-5 ma
HA-5 Electrical Specifications PARAMETER V SUPPLY = ±15V, R L = 1kΩ, C L < 1pF, Unless Otherwise Specified (Continued) Power Supply Rejection Ratio (Note 9) Full 7-7 - db 3. R L = 1kΩ, V O = ±1V.. V CM = ±1V. 5. V O = 9mV.. A V = 1. Slew Rate 7. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------. πv. Refer to Test Circuits section of the data sheet. PEAK 9. V SUPPLY = +5V, -15V and +15V, -5V. 1. Guaranteed range for output voltage is ±1V. Functional operation outside of this range is not guaranteed. Test Circuits and Waveforms TEMP ( o C) HA-5- HA-5-5 MIN TYP MAX MIN TYP MAX UNITS V IN + - 9 1 V OUT 11. A V = +1. 1. C L 1pF. FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT A B Vertical Scale: A =.5V/Div., B = 5.V/Div. Horizontal Scale: 5ns/Div. Vertical Scale: Input = 1mV/Div.; Output = 5mV/Div. Horizontal Scale: ns/div. LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE INPUT 5Ω SETTLE POINT Ω - +.1µF 1µF.1µF 1µF kω 5kΩ OUTPUT PROBE MONITOR 13. A V = -1. 1. Load Capacitance should be less than 1pF. Turn on time delay typically ns. 15. It is recommended that resistors be carbon composition and the feedback and summing network ratios be matched to.1%. 1. SETTLE POINT (Summing Node) capacitance should be less than 1pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 5 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor. FIGURE. SETTLING TIME TEST CIRCUIT 3
HA-5 Schematic Diagram R 3 R 1 R Q P1 Q P R 3 R Q P Q P19 R 13 R Q P17 R5 Q P5 Q P Q P5 R Q N C 1 C R C Q N1 Q N7 Q N9 + INPUT R R 7 Q P R 1 OUTPUT Q P3 QN1 R R 9 Q N1 R 19 - INPUT Q P3 Q P Q P11 R 1 Z 1 Q N5 Q N1 R 5 R 1 Q N Q N15 R 1 Q N13 D Z1 Q N1 Q N1 D Z R 11 R1 Q N9 R 1 R 15 R 17 Typical Applications - + K HA-5 K OFFSET ADJUST C 1 (NOTE 1) 1K 1K R 5 (NOTE 19) - + HA-5 1K C F (NOTE 17).1µF R 3 K R 1 K R K SIGNAL OUT NOTE: With one HA-5 and two low capacitance switching diodes, signals exceeding 1MHz can be separated. This circuit is most useful for full wave rectification, AM detectors or sync generation. R K 17. Used for experimental purposes. C F 3pF. 1. C 1 is optional (.1µF.1µF ceramic). 19. R 5 is optional and can be utilized to reduce input signal amplitude and/or balance input conditions. R 5 = 5Ω to 1kΩ. FIGURE 3. WIDEBAND SIGNAL SPLITTER FIGURE. BOOTSTRAPPING FOR MORE OUTPUT CURRENT AND VOLTAGE SWING Refer to Application Note AN51 For Further Application Information.
HA-5 Typical Performance Curves CLOSED LOOP GAIN (db) 1 9 7 5 3 1-1 1 1K 1K 1K 1M 1M 1M FREQUEY (Hz) OUTPUT VOLTAGE SWING (V P-P ) 1 1 V S = ±15V V S = ±1V V S = ±5V 1K 1K 1K 1M 1M 1M FREQUEY (Hz) FIGURE 5. CLOSED LOOP FREQUEY RESPONSE FIGURE. OUTPUT VOLTAGE SWING vs FREQUEY OUTPUT VOLTAGE SWING (V P-P ) 1 1 1K 1.K NORMALIZED PARAMETERS REFERRED TO VALUES AT 5 o C 1. 1.3 1. 1.1 BANDWIDTH 1..9 SLEW RATE..7. - - 1 1 RESISTAE (Ω) TEMPERATURE ( o C) FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTAE FIGURE. NORMALIZED AC PARAMETERS vs TEMPERATURE OUTPUT VOLTAGE STEP (V) 1 1mV - - - - -1 1mV 1 1 SETTLING TIME (ns) 1mV 1mV SUPPLY CURRENT (ma) 1 1 - - 1 1 TEMPERATURE ( o C) V S = ±15V V S = ±5V FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES FIGURE 1. POWER SUPPLY CURRENT vs TEMPERATURE 5
HA-5 Typical Performance Curves (Continued) INPUT BIAS CURRENT (µa) 1 1 1 - - 1 1 TEMPERATURE ( o C) OFFSET VOLTAGE BIAS CURRENT FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE 7 5 3 1 V IO OFFSET VOLTAGE (mv) NOISE VOLTAGE (nv/ Hz) 5 15 1 5 1 R SOURCE = Ω, V S = ±15 VOLTAGE NOISE CURRENT NOISE 1 1K 1K 1K FREQUEY (Hz) FIGURE 1. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUEY 5 3 1 NOISE CURRENT (pa/ Hz) +µv +3µV +µv 1 1 V S = ±15, R L = 1K +1µV µv -1µV -µv -3µV CMRR (db) -µv Vertical Scale: 1mV/Div. Horizontal Scale: 5ms/Div. 1K 1K 1K 1M 1M FREQUEY (Hz) FIGURE 13. BROADBAND NOISE (.1Hz TO 1MHz) FIGURE 1. COMMON MODE REJECTION RATIO vs FREQUEY 1 1 PSRR (db) POSITIVE SUPPLY NEGATIVE SUPPLY OPEN LOOP GAIN (db) PHASE GAIN 5 9 135 1 PHASE (DEGREES) 1K 1K 1K 1M FREQUEY (Hz) 1M -1 1 1K 1K 1K 1M 1M 1M FREQUEY (Hz) 5 FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUEY FIGURE 1. OPEN LOOP GAIN/PHASE vs FREQUEY
HA-5 Die Characteristics DIE DIMENSIONS: mils x 7 mils x 19 mils 1575 µmx 193µm x 3µm METALLIZATION: Type: Al, 1% Cu Thickness: 1kÅ ±kå PASSIVATION: SUBSTRATE POTENTIAL (Powered Up): TRANSISTOR COUNT: 3 PROCESS: Bipolar Dielectric Isolation Type: Nitride (Si 3 N ) over Silox (SiO, 5% Phos.) Silox Thickness: 1kÅ ±kå Nitride Thickness: 3.5kÅ ±1.5kÅ Metallization Mask Layout HA-5 OUTPUT - IN + IN 7
HA-5 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 -C- -A- N 1 3 N/ B D e D1 E1 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y1.5M-19. 3. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 95.. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 inch (.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed.1 inch (.5mm). 9. N is the maximum number of terminal positions. 1. Corner leads (1, N, N/ and N/ + 1) for E.3, E1.3, E1.3, E.3, E. will have a B1 dimension of.3 -.5 inch (.7-1.1mm). -B- A1.1 (.5) M C A A L B S A e C E C L e A C e B E1.3 (JEDEC MS-1-AA ISSUE D) 1 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.1-5.33 A1.15 -.39 - A.115.195.93.95 - B.1..35.55 - B1.5.7 1.15 1.77 C..1..355 - D.735.775 1. 19. 5 D1.5 -.13-5 E.3.35 7..5 E1...1 7.11 5 e.1 BSC.5 BSC - e A.3 BSC 7. BSC e B -.3-1.9 7 L.115.15.93 3.1 N 1 1 9 Rev. 1/93
HA-5 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b ccc M bbb S b C A - B C A - B S D A A e D S 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (1, N, N/, and N/+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b. 5. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners.. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y1.5M - 19. 1. Controlling dimension: IH. E L M c1 ea/ S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A -D- -A- Q -C- A -Bα S ea c D S (c) F1.3 MIL-STD-135 GDIP1-T1 (D-1, CONFIGURATION A) 1 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -. - 5. - b.1..3. b1.1.3.3.5 3 b.5.5 1.1 1.5 - b3.3.5.5 1.1 c..1.. c1..15..3 3 D -.75-19.9 5 E..31 5.59 7.7 5 e.1 BSC.5 BSC - ea.3 BSC 7. BSC - ea/.15 BSC 3.1 BSC - L.15. 3.1 5. - Q.15..3 1.5 S1.5 -.13-7 α 9 o 15 o 9 o 15 o - aaa -.15 -.3 - bbb -.3 -.7 - ccc -.1 -.5 - M -.15 -.3, 3 N 1 1 Rev. /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9