OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 888TERSIL or www.intersil.com/tsc HA595 Data Sheet November 9, 2 FN29.6 5MHz, Fast Settling Operational Amplifier The HA595 is a operational amplifier featuring a combination of speed, precision, and bandwidth. Employing monolithic bipolar construction coupled with Dielectric Isolation, this device is capable of delivering 2V/µs slew rate with a settling time of 7ns (.%, 5V output step). This truly differential amplifier is designed to operate at gains 5 without the need for external compensation. Other outstanding features are 5MHz gain bandwidth product and 6.5MHz full power bandwidth. In addition to these dynamic characteristics, this amplifier also has excellent input characteristics such as 3mV offset voltage and 6.nV/ Hz input voltage noise at khz. With 2V/µs slew rate and 7ns settling time, the HA595 is an ideal output amplifier for accurate, high speed D/A converters or the main components in high speed sample/hold circuits. The 595 is also ideally suited for a variety of pulse and wideband video amplifiers. Please refer to Application Notes AN525 and AN526 for some of these application designs. At temperatures above 75 o C a heat sink is required for the HA595 (see Note 2 and Application Note AN556). Part Number Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # HA5955 to 75 Ld CERDIP F.3 Features Fast Settling Time (.%)..................... 7ns Very High Slew Rate...................... 2V/µs Wide GainBandwidth (A V 5)............... 5MHz Full Power Bandwidth...................... 6.5MHz Low Offset Voltage........................... 3mV Input Noise Voltage...................... 6nV/ Hz Bipolar D.I. Construction Applications Fast, Precise D/A Converters High Speed SampleHold Circuits Pulse and Video Amplifiers Wideband Amplifiers Pinout 2 3 5 HA595 (CERDIP) TOP VIEW 3 2 V V 6 9 7 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888TERSIL or 327273 Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Harris Corporation 998. Copyright Intersil Americas Inc. 22, 2. All Rights Reserved
Absolute Maximum Ratings T A =25 o C Thermal Information Supply Voltage (V to V).............................. 35V Differential Input Voltage............................... 6V Output Current............................... 5mA (Peak) Operating Conditions Temperature Range........................... o C to 75 o C Thermal Resistance (Typical, Note 2) θ JA ( o C/W) θ JC ( o C/W) CERDIP Package................... 75 2 Maximum Junction Temperature (Hermetic Package, Note )..75 o C Maximum Storage Temperature Range.......... 65 o C to 5 o C Maximum Lead Temperature (Soldering s)............ 3 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.. Heat sinking may be required, especially at T A 75 o C. 2. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±5V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP ( o C) M TYP MAX UNITS PUT CHARACTERISTICS Offset Voltage 25 3 6 mv Full mv Average Offset Voltage Drift Full 2 µv/ o C Bias Current 25 5 5 µa Full 2 µa Offset Current 25 µa Full 6 µa Input Resistance 25 kω Input Capacitance 25 pf Common Mode Range Full ±5 V Input Noise Current f = khz, R G = Ω 25 5 pa/ Hz Input Noise Voltage f = khz, R G = Ω 25 6 nv/ Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) 25 3 kv/v Full 5 kv/v Common Mode Rejection Ratio V CM = ±5V Full 7 95 db Minimum Stable Gain 25 5 V/V GainBandwidthProduct V = 9mV, A V = 25 5 MHz PUT CHARACTERISTICS Output Voltage Swing (Note 3) Full ±5 ±8 V Output Current (Note 3) 25 ±25 ±3 ma Output Resistance Open Loop 25 3 Ω Full Power Bandwidth (Notes 3, ) 25 5 6.5 MHz TRANSIENT RESPONSE (Note 5) Rise Time 25 3 8 ns Overshoot 25 8 % Slew Rate 25 6 2 V/µs Settling Time (Note 5) 5V Step to.% 25 7 ns 5V Step to.% 25 ns 2.5V Step to.% 25 5 ns 2.5V Step to.% 25 8 ns POWER SUPPLY CHARACTERISTICS Supply Current Full 9 28 ma 2 FN29.6 November 9, 2
Electrical Specifications PARAMETER TEST CONDITIONS TEMP ( o C) M TYP MAX UNITS Power Supply Rejection Ratio V S = ±V to ±2V Full 7 9 db 3. R L = 2Ω, C L < pf, V = ±5V. Slew Rate. Full power bandwidth guaranteed based on slew rate measurement using: FPBW =. 2πV 5. Refer to Test Circuits section of the data sheet. PEAK Test Circuits and Waveforms V SUPPLY = ±5V, Unless Otherwise Specified (Continued).6kΩ Ω 2Ω 6. A V = 5. 7. C L < pf. FIGURE. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT 5V V 9% 5V % V V V V V Vertical Scale: V = 2.V/Div., V =./Div. Horizontal Scale: ns/div. LARGE SIGNAL RESPONSE Vertical Scale: V = 5mV/Div., V = mv/div. Horizontal Scale: ns/div SMALL SIGNAL RESPONSE V.µF SETTLE POT Ω kω V 2kΩ 5kΩ µf.µf µf PROBE MONITOR 8. A V = 5. 9. Load Capacitance should be less than pf.. It is recommended that resistors be carbon composition and that feedback and summing network ratios be matched to.%.. Settle Point (Summing Node) capacitance should be less than pf. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S3A sampling heads is recommended as a settle point monitor. FIGURE 2. SETTLG TIME TEST CIRCUIT 3 FN29.6 November 9, 2
Schematic Diagram V R R 2 R 3 R Q P2 Q P Q P6 R 28 R 6 Q P23 Q N56 Q P3 Q P5 Q N22 C C 2 R 7 R 8 R 29 Q P2 Q N2 R 9 Q N Q N2 Q N9 C 3 Q N5 Q P9 R 2 R 25 Q N53 Q P32 Q P33 D 3 D 5 R 32 Q P Q P35 D 37 Q P36 R 26 R 27 D 52 Q N39 D 38 Q N Q P7 Q P8 R 33 Q P5 D Q N2 Q N3 R Q N8 R R 2 Q P55 Q N9 Q N Q N5 QN6 Q P6 Q N7 R 3 Q P5 R Q N Q N Q N2 Q N7 Q N3 Q N8 R 5 R 6 R 7 R 8 R 3 R 3 V Application Information Power Supply Decoupling Although not absolutely necessary, it is recommended that all power supply lines be decoupled with.µf ceramic capacitors to ground. Decoupling capacitors should be located as near to the amplifier terminals as possible. Stability Considerations HA595 is stable at gains > 5. Gains < 5 are covered below. Feedback resistors should be of carbon composition located as near to the input terminals as possible. Output Short Circuit HA595 does not have output short circuit protection. Short circuits to ground can be tolerated for approximately seconds. Short circuits to either supply will result in immediate destruction of the device. Heavy Capacitive Loads When driving heavy capacitive loads (>pf) a small resistor (Ω) should be connected in series with the output and inside the feedback loop. Wiring Considerations Video pulse circuits should be built on a ground plane. Minimum point to point connections directly to the amplifier terminals should be used. When ground planes cannot be used, good single point grounding techniques should be applied. FN29.6 November 9, 2
Typical Applications (Also see Application Notes AN525 and AN526) pf C (NOTE) 2Ω kω (NOTE) R F 2Ω R F 75Ω (NOTE) kω (NOTE) PUT PUT PUT PUT Vertical Scale: 2V/Div. Horizontal Scale: ns/div. Vertical Scale: 2V/Div. Horizontal Scale: ns/div NOTE: Values were determined experimentally for optimum speed and settling time. R F and C should be optimized for each particular application to ensure best overall frequency response. FIGURE 3. SUGGESTED COMPENSATION FOR NONVERTG UNITY GA AMPLIFIER kω PUT kω 2Ω PUT Vertical Scale: 2V/Div. Horizontal Scale: 5ns/Div. FIGURE. SUGGESTED COMPENSATION FOR VERTG UNITY GA AMPLIFIER V 2Ω µf µf.6kω 2Ω 75Ω 5Ω Ω HA595 2Ω µf V HA533 µf 5kΩ 5Ω kω FIGURE 5. VIDEO PULSE AMPLIFIER/75Ω COAXIAL DRIVER FIGURE 6. VIDEO PULSE AMPLIFIER COAXIAL LE DRIVER 5 FN29.6 November 9, 2
Typical Performance Curves V S = ±5V, T A = 25 o C, Unless Otherwise Specified 5 2. PUT BIAS CURRENT (µa) 3 2 OFFSET VOLTAGE BIAS CURRENT.6.2.8. OFFSET VOLTAGE (mv) OPEN LOOP VOLTAGE GA (db) 8 6 2 PHASE GA 5 9 35 8 PHASE (DEGREES) 8 8 2 6 TEMPERATURE ( o C) FIGURE 7. PUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE 2 225 K K K M M M FREQUEY (Hz) FIGURE 8. OPEN LOOP FREQUEY RESPONSE 8.2 PUT VOLTAGE SWG (V PP ) 6 2 8 6 NORMALIZED PARAMETERS REFERRED TO VALUES AT 25 o C...9.8.7 BANDWIDTH SLEW RATE K K K M FREQUEY (Hz) M M 8 8 2 6 TEMPERATURE ( o C) FIGURE 9. PUT VOLTAGE SWG vs FREQUEY FIGURE. NORMALIZED AC PARAMETERS vs TEMPERATURE.2 NORMALIZED VALUE REFERRED TO LOAD CAPACITAE EQUAL TO pf...9.8 BANDWIDTH SLEW RATE LOAD CAPACITAE (pf) 2 25 PUT NOISE VOLTAGE (nv/ Hz) PUT NOISE VOLTAGE PUT NOISE CURRENT K K FREQUEY (Hz) K PUT NOISE CURRENT (pa/ Hz) FIGURE. NORMALIZED AC PARAMETERS vs LOAD CAPACITAE FIGURE 2. PUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUEY 6 FN29.6 November 9, 2
Typical Performance Curves V S = ±5V, T A = 25 o C, Unless Otherwise Specified (Continued) PUT VOLTAGE SWG (V) 2 8 6 2 PUT VOLTAGE STEP (V) 5 2.5 2.5 5 5mV 5mV.5mV.5mV 2 6 8 K.2K LOAD RESISTAE (Ω) 2 3 5 6 7 8 9 SETTLG TIME (ns) FIGURE 3. PUT VOLTAGE SWG vs LOAD RESISTAE FIGURE. SETTLG TIME FOR VARIOUS PUT STEP VOLTAGES COMMON MODE REJECTION RATIO (db) 2 8 6 2 K K FREQUEY (Hz) K M POWER SUPPLY REJECTION RATIO (db) 2 8 6 2 K NEGATIVE SUPPLY POSITIVE SUPPLY K FREQUEY (Hz) K M FIGURE 5. COMMON MODE REJECTION RATIO vs FREQUEY FIGURE 6. POWER SUPPLY REJECTION RATIO vs FREQUEY POWER SUPPLY CURRENT (ma) 2 2 6 2 8 V SUPPLY = ±5V V SUPPLY = ±V 8 8 TEMPERATURE ( o C) 2 6 FIGURE 7. POWER SUPPLY CURRENT vs TEMPERATURE 7 FN29.6 November 9, 2
Die Characteristics DIE DIMENSIONS: 5 mils x 88 mils x 9 mils 36µm x 22µm x 83µm METALLIZATION: Type: Al, % Cu Thickness: 6kÅ ±2kÅ PASSIVATION: SUBSTRATE POTENTIAL (Powered Up): V TRANSISTOR COUNT: 9 PROCESS: Bipolar Dielectric Isolation Type: Nitride (Si 3 N ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 2kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±.5kÅ Metallization Mask Layout HA595 V PUT V 8 FN29.6 November 9, 2
Ceramic DualInLine Frit Seal Packages (CERDIP) BASE PLANE SEATG PLANE S b2 ccc M bbb S b C A B C A B S D A A e D S. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (, N, N/2, and N/2) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for offcenter lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y.5M 982.. Controlling dimension: IH. E L M c ea/2 S D S aaa M C A B LEAD FISH BASE METAL b M (b) SECTION AA D A Q C A Bα S ea c D S (c) F.3 MILSTD835 GDIPT (D, CONFIGURATION A) LEAD CERAMIC DUALLE FRIT SEAL PACKAGE IHES MILLIMETERS SYMBOL M MAX M MAX NOTES A.2 5.8 b..26.36.66 2 b..23.36.58 3 b2.5.65..65 b3.23.5.58. c.8.8.2.6 2 c.8.5.2.38 3 D.785 9.9 5 E.22.3 5.59 7.87 5 e. BSC 2.5 BSC ea.3 BSC 7.62 BSC ea/2.5 BSC 3.8 BSC L.25.2 3.8 5.8 Q.5.6.38.52 6 S.5.3 7 α 9 o 5 o 9 o 5 o aaa.5.38 bbb.3.76 ccc..25 M.5.38 2, 3 N 8 Rev. /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN29.6 November 9, 2