Iteratioal Joural of Pure ad Applied Mathematics Volume 118 No. 18 2018, 4053-4060 ISSN: 1311-8080 (prited versio); ISSN: 1314-3395 (o-lie versio) url: http://www.ijpam.eu ijpam.eu Performace aalysis of NAND ad NOR logic usig 14m techology ode 1 Priyamaga Bhardwaj, 2 P. Uma Sathyakam, 3 M.Marimuthu ad 4 S.Balamuruga 1,2,3,4 SELECT, VIT Uiversity, Vellore 14. Abstract We carried out performace aalysis of NAND ad NOR logic gates at 14m techology ode, to fid out the propagatio delay ad the average power dissipatio as show by the cosidered gates. We have carried out the simulatios for iput voltages of 0.8, 0.6, 0.45, 0.3 ad 0.2 volts. We simulate the give gate coditios usig Silvaco SmartSPICE. The results show that i both of these logic gates whe the iput voltage is higher, we face more power cosumptio, but the propagatio delay is lesser. So for optimum performace, some midway combiatio ca be appropriately cosidered o a case-to-case basis. Key Words NAND logic, NOR logic, VLSI, propagatio delay, power dissipatio. 1. INTRODUCTION NAND ad NOR logic gates have bee i existece sice a few years ow, to aid i differet electrical ad electroics applicatios. Applicatios rage from simple academic ad research purposes, to heavy idustrial uses, to sesitive ad critical defese electroic eeds. Hece it becomes very importat that they are desiged, ad thereo utilized to give the most effective, cost-friedly ad efficiet performaces [4]. The logic gates are programmable at various techology odes such as 10m, 12m, 14m, 16m, 20m etc. For our research, we have cosidered the stadard 14m techology ode. I Sectio II, we have preseted the NAND gate desig ad the NOR gate desig based o which the SmartSPICE code was costructed. I Sectio III, we have provided the circuit validatio, which icludes the timig diagrams derived by applyig the values of the truth tables of the respective gates. I Sectio IV, we have carried out the performace aalysis of the circuits, which icludes the propagatio delay ad power dissipatio. This sectio also icludes the simulatio plots ad the tabulated readigs. Sectio V gives the cocludig remarks. 2. CIRCUIT DESIGN The Circuit Desig of the two gates i CMOS techology is cosidered, with M1 ad M2, M3 ad M4 deotig the NMOS ad PMOS gates respectively. The NAND Gate desig [10, 11, 12] cosidered is as follows: 4053
Iteratioal Joural of Pure ad Applied Mathematics Fig. 1 NAND Gate desig cosidered i this work. The NOR Gate desig cosidered [10, 12] is as follows: Fig. 2 NOR Gate desig cosidered i this work. The NAND ad NOR gates were hece costructed i the CMOS cofiguratio, ad the circuit desig variables which will later be used i costructig the SmartSPICE codes. 3.CIRCUIT VALIDATION By supplyig the truth table logic gate iputs i the simulatio, we obtai the timig diagrams for circuit validatio as follows: 4054
Iteratioal Joural of Pure ad Applied Mathematics Fig. 3 Output waveform of NOR gate Fig. 4 Output waveform of NAND gate The timig diagrams of the NAND ad NOR gates were hece obtaied by providig the logic gate truth table values, i plots havig time versus v(out) i the axes. 4.CIRCUIT ANALYSIS For the performace aalysis [5, 13] of the aforemetioed NAND ad NOR logic gates, we maily gauge them based o the propagatio delays show by them ad also the average power cosumed [6] by them. These gates are desiged usig trasistors. For simulatios o these gates, we have used SmartSPICE. We have supplied varyig iput voltages (V dd ) of 0.2V, 0.3V, 0.45V, 0.6V ad 0.8V, which has resulted i differet readigs of propagatio delays ad average power cosumed [11,14]. The SmartSPICE code for NAND gate was costructed as follows:.temp 27.param Supply=0.2.iclude '14fet_hp.lib'.iclude '14pfet_hp.lib'.optios post.global vdd gd vdd vdd gd 'supply' m1 out ia vdd vdd pfet l=3e-008 m2 out ib vdd vdd pfet l=3e-008 m3 out ia d gd fet l=3e-008 m4 d ib gd gd fet l=3e-008 va ia gd pulse(0 'supply' 1 0.1 0.1 10 20) 4055
Iteratioal Joural of Pure ad Applied Mathematics vb ib gd pulse(0 'supply' 1 0.1 0.1 10 20).tra 0.1s 90s.probe v(out).measure prop_delay + TRIG v(ia) VAL='Supply/2' RISE=1 + TARG v(out) VAL='Supply/2' FALL=1.measure output_power AVG power FROM=1 TO=10.ed The code for the NOR gate is:.temp 27.param Supply=0.3.iclude '14fet_hp.lib'.iclude '14pfet_hp.lib'.optios post.global vdd gd vdd vdd gd 'supply' m1 d ia vdd vdd pfet l=3e-008 m2 out ib d vdd pfet l=3e-008 m3 out ia gd gd fet l=3e-008 m4 out ib gd gd fet l=3e-008 va ia gd pulse(0 'supply' 1 0.1 0.1 10 20) vb ib gd pulse(0 'supply' 1 0.1 0.1 10 20).tra 0.1s 90s.probe v(out).measure prop_delay + TRIG v(ia) VAL='Supply/2' RISE=1 + TARG v(out) VAL='Supply/2' FALL=1.measure output_power AVG power FROM=1 TO=10.ed For eergizig the two logic gates to result i plots, we simulate the gates for ia vs. out ; while varyig the V dd i each case ad i the two differet logic gates. NAND Gate with 0.3V iput V dd [8]. Fig. 5 Plot for NAND gate with 0.3V iput V dd. 4056
Iteratioal Joural of Pure ad Applied Mathematics Fig. 6 Plot for NAND gate with 0.2V iput V dd. Fig. 7 Plot for NOR gate with 0.3V iput V dd. Fig. 8 Plot for NOR gate with 0.2V iput V dd. Also we obtai the various readigs of the propagatio delays ad average power cosumed [3,7] with a fixed techology ode & varyig V dd after simulatios; ad they are tabulated as follows: 4057
Iteratioal Joural of Pure ad Applied Mathematics TABLE I Performace factors of NOR Gate usig 14m techology ode Vd d Delay (ps) Average power (W) Remar ks 0.8-7.188 24.59 5,10 0.6-2.248 10,20 0.0247 0.4 0.694 0.344 10,20 5 0.3 31.99 0.567 10,20 0.2 81.86 0.479 10,20 Descriptio Glitch at fallig edge More glitch. TABLE II Performace factors of NAND Gate usig 14m techology ode V dd Delay Average Remar Descriptio (ps) power (W) ks 0.8 7.825 35.137 5,10 0.6 1.229 1.508 10,20 0.4 5 1.783 0.306 10,20 0.3 41.29 0.319 10,20 Glitch at fallig edge 0.2 237.37 0.407 10,20 More glitch. It ca be see that as the iput voltage (V dd ) was decreased from 0.8V to 0.2V, the propagatio delays icreased expoetially for the two gates. But the average power cosumed decreased for both the gates. Our simulatios were doe cosiderig ambiet temperature as 27 C. We had also cosidered PTM High Performace (PTM_hp) [15]. 5.CONCLUSIONS I this paper we have doe the performace characteristics of the give two gates uder some imposed coditios. Cosiderig these coditios, the efficiecy of the assumed techology ode (14m) was calculated. Whe the Vdd was 0.3V for both the gates, glitches were observed at the fallig edges i the plots. Also at Vdd=0.2V, we experieced more glitch. So to strike a proper balace betwee the average power cosumed ad the propagatio delay experieced, some set of values midway has to be take ito cosideratio o a case-to-case basis[9]. Further scope lies i simulatig i differet temperatures, ad also takig ito cosideratio differet techology odes. Ad further simulatios ca be udertake for PTM Low Performace (PTM_lp) ad so o. REFERENCES [1] Chi, P., Su, J. ad Zhog, X., Aalysis ad Desig of High Performace ad Low Power Curret Mode Logic CMOS. [2] da Silva, D.N., Reis, A.I. ad Ribas, R.P., 2009. CMOS logic gate performace variability related to trasistor etwork arragemets. Microelectroics Reliability, 49(9), pp.977-981. [3] Sakar, P.G. ad Udhayakumar, K., 2014. MOSFET-like CNFET based logic gate library for low-power applicatio: a comparative study. Joural of Semicoductors, 35(7), p.075001. 4058
Iteratioal Joural of Pure ad Applied Mathematics [4] Hajare, R., Lakshmiarayaa, C., Sumath, S.C. ad Aish, A.R., 2015, December. Desig ad evaluatio of FiFET based digital circuits for high speed ICs. I Emergig Research i Electroics, Computer Sciece ad Techology (ICERECT), 2015 Iteratioal Coferece o (pp. 162-167). IEEE. [5] Vo Arim, K., Augedre, E., Pacha, C., Schulz, T., Sa, K.T., Bauer, F., Nackaerts, A., Rooyackers, R., Vadeweyer, T., Degroote, B. ad Collaert, N., 2007, Jue. A low-power multi-gate FET CMOS techology with 13.9 ps iverter delay, large-scale itegrated high performace digital circuits ad SRAM. I 2007 IEEE Symposium o VLSI Techology (pp. 106-107). IEEE. [6] Yag, W.B., Li, Y.Y. ad Lo, Y.L., 2014, April. Aalysis ad desig cosideratios of static CMOS logics uder process, voltage ad temperature variatio i 90m CMOS process. I Iformatio Sciece, Electroics ad Electrical Egieerig (ISEEE), 2014 Iteratioal Coferece o (Vol. 3, pp. 1653-1656). IEEE. [7] Gupta, P. ad Islam, A., 2014, February. Robustess study ad CNFET realizatio of optimal logic circuit for ultralow power applicatios. I Sigal Processig ad Itegrated Networks (SPIN), 2014 Iteratioal Coferece o (pp. 618-623). IEEE. [8] Bhuvaa, R., Prabhu, V. ad Bibi, M.R., 2016. Cotet Addressable Memory performace Aalysis usig NAND Structure FiFET. Global Joural of Pure ad Applied Mathematics, 12(1), pp.1077-1084. [9] Gummalla, S., Subramaiam, A.R., Cao, Y. ad Chakrabarti, C., 2012, March. A aalytical approach to efficiet circuit variability aalysis i scaled CMOS desig. I Thirteeth Iteratioal Symposium o Quality Electroic Desig (ISQED) (pp. 641-647). IEEE. [10] Veugopal, R., Chakravarthi, S. ad Chidambaram, P.R., 2006. Desig of CMOS trasistors to maximize circuit FOM usig a coupled process ad mixed-mode simulatio methodology. IEEE electro device letters, 27(10), pp.863-865. [11] Kim, S., Kwo, D.W., Kim, J.H., Park, E., Lee, J., Park, T., Lee, R. ad Park, B.G., 2016, Jue. MOSFET-TFET hybrid NAND/NOR cofiguratio for improved AC switchig performace. I Silico Naoelectroics Workshop (SNW), 2016 IEEE (pp. 114-115). IEEE. [12] Nadyala, V.R. ad Mahapatra, K.K., 2016. A Circuit Techique for Leakage Power reductio i CMOS VLSI Circuits. [13] Mahmoudi, H., Widbacher, T., Sverdlov, V. ad Selberherr, S., 2013, September. Performace aalysis ad compariso of two 1T/1MTJ-based logic gates. I 2013 Iteratioal Coferece o Simulatio of Semicoductor Processes ad Devices (SISPAD) (pp. 163-166). IEEE. [14] Raja, T., Agrawal, V.D. ad Bushell, M.L., 2009. Variable iput delay cmos logic for low power desig. IEEE trasactios o very large scale itegratio (VLSI) systems, 17(10), pp.1534-1545. [15] http://ptm.asu.edu/ [Available Olie] 4059
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