Wide frequency range duty cycle correction circuit for DDR interface Dongsuk Shin a), Soo-Won Kim, and Chulwoo Kim b) Dept. of Electronics and Computer Engineering, Korea University, Anam-dong, Seongbuk-Gu, Seoul 136 701, Korea a) sds@kilby.korea.ac.kr b) ckim@korea.ac.kr Abstract: The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500 MHz to 2 GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18 um CMOS technology. Keywords: duty cycle correction, duty detector, double date rate Classification: Integrated circuits References [1] S. J. Jang, Y. H. Jun, J. G. Lee, and B. S. Kong, ASMD with duty cycle correction scheme for high-speed DRAM, Electron. Lett., vol. 37, pp. 1004 1006, 2001. [2] C. Jang, C. Yoo, J. J. Lee, and J. Kih, Digital delay locked loop with open-loop digital duty cycle corrector for 1.2 GbMpin double data-rate SDRAM, IEEE European Solid-State Circuits Conference, pp. 379 382, 2004. [3] D. U. Lee, H. W. Lee, K. C. Kwean, Y. K. Choi, H. U. Moon, S. W. Kwack, S. D. Kang, K. W. Kim, Y. J. Kim, Y. J. Choi, P. Moran, J. H. Ahn, and J. S. Kih, A 2.5 Gb/s/pin 256 Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop digital DLL, Dig. Tech. Pprs, International Solid-State Circuits Conference, vol. 49, pp. 160 161, 2006. [4]J.T.Kwak,C.K.Kwon,K.W.Kim,S.H.Lee,andJ.Kih, Alow cost high performance register-controlled digital DLL for 1 Gbps x32 DDR SDRAM, Dig. Tech. Pprs, VLSI Circuits Symp., pp. 283 284, 2003. [5] Y. C. Jang, S. J. Bae, and H. J. Park, CMOS digital duty cycle correction circuit for multi-phase clock, Electron. Lett., vol. 39, no. 19, 2003. [6] K. Agarwal and R. Montoye, A duty-cycle correction circuit for highfrequency clocks, Dig. Tech. Pprs, VLSI Circuits Symp., pp. 106 107, 2003. 254
1 Introduction As broadband data communications and advanced multimedia technologies have gained wide spread acceptance in the consumer market recently, there is an increasing need for high-performance, high-density memories. In highspeed interface systems, double data rate synchronous DRAMs (DDR SDRAMs) use both rising and falling edges of the clock signal, which doubles the data bandwidth compared to conventional schemes that use only rising edges. In such DDR memories the clock duty ratio ideally should be 50% to avoid corrupt data transmission caused by inappropriate data windows, leading to data rate reduction. Hence, in high-speed DDR memories, a DCC circuit is often required to adjust the clock duty ratio to 50%. Conventional DCC schemes are categorized as either digital or analog. In analog DCC, the duty ratio differences of the signal from 50% duty cycle are averaged in time and the DCC circuit stores this value as a voltage level in a capacitor [1]. However, in this method, control information is lost during a power down mode. To store the control information in digital domain and guarantee a stable operation over process, voltage and temperature (PVT) variations, several digital DCC circuits have been proposed [2, 3, 4, 5]. A digital DCC circuit proposed by Jang achieves 50% duty cycle output by interpolating the input clock with a half-cycle-delayed, inverted version of itself [2, 3, 4]. However, the output clock phase may change if the duty ratio of the input clock changes because the output is interpolated by both rising and falling edges of input clock. As a result, the interpolated output phase of DLL may re-lock whenever the duty ratio of input clock change. Furthermore, the application of this scheme with increasing clock frequency requires shorter delay cells in greater numbers to achieve the finer resolution necessary. The conventional digital DCC circuits in [3, 4] consume more power and occupies a large chip area due to using one more DLL block to make a half cycle delayed clock of the input clock. Another digital DCC circuit combines the rising edges of input clock and half-cycle-delayed clock [5, 6]. However, the DCC circuits limit frequency range because it needs many delay line to delay half-cycle-delayed clock at low frequency. The digital DCC circuit proposed in this paper makes 50% duty ratio output clock from an arbitrary duty ratio input clock without changing the output clock phase, and so is independent of dynamic duty ratio changes. It can also operate over a wide frequency range of 500 MHz to 2 GHz. 2 Concept of proposed digital DCC Figure 1 shows the block and timing diagrams of the proposed digital DCC. The input clock (In Clk) feeds a delay line which generates the output clock (Out Clk). Due to the proposed unit delay cell of the delay line, when the duty ratio of In Clk is changing, the rising edge phase of Out Clk is kept constant but the falling edge phase of Out Clk is varied by counting codes of the Up/Down Counter as shown in Fig. 1 (b). Figure 2 (a) shows the schematic of the proposed unit delay cell. Each unit delay cell of a delay line 255
Fig. 1. Block and timing diagram of the proposed DCC circuit: (a) Block diagram, (b) Timing diagram. has six switches that have equivalent phase differences. To keep a constant phase of rising-edge of Out Clk, the first inverter of the unit delay cell has only PMOS switches (S1 S3) and the second inverter of the unit delay cell has only NMOS switches (S4 S6), which do not affect the delay of rising edge of Out Clk. The number of unit delay cells basically determines the counting number. The Duty Detector consists of a Control Block, two Time-to-Voltage Converters (TVCs) and two comparators. The Control Block generates HClk, LClk, pre and com signals that are used to control the TVC and two comparators. HClk and LClk signals are Hi during the Hi and Lo phases of the Out Clk, respectively. The TVC and two comparators monitor the duty cycle information of Out Clk and generate up and down signals to operate the Up/Down Counter. As shown in Fig. 2 (b), the TVC is controlled by pre and either HClk or LClk. The TVC operates as follows: The capacitor of the TVC, CL, is precharged first during the low duration of pre, andthen discharged for the high duration of HClk or LClk as Iref flows constantly through the NMOS transistors. Then, the outputs of the two TVCs (VH and VL) feed the comparators as shown in Fig. 1 (a). The difference (Vx) 256
Fig. 2. Block Unit delay cell, TVC and timing diagram: (a) Structure of unit delay cell, (b) Structure of TVC, (c) Timing diagram of duty detector. between VH and VL is expressed by Iref TL TL V X = (1) CL Hysteresis of the comparator plays an important role in deciding the DCC locking zone that determines the duty cycle of Out Clk. The comparator with hysteresis detects whether the difference between the high durations of HClk and LClk is less than a switch delay or not. By using two hysteretic comparators the range of DCC locking zone can be decided. The outputs of the two comparators, up and down, feed the Up/Down Counter which keeps counting up or down until Out Clk reaches 50% duty cycle. If the duty cycle of Out Clk is about 50%, the Up/Down Counter stops counting and thus the digital DCC is locked. To make the operation range of 500 MHz to 2 GHz, the unit delay cell should have a 10 ps resolution and a delay line should have ten stage unit delay cells. For 6-bit counting, the last unit delay cell of a delay line uses only four switches. As a result, the 6-bit counter is used and the proposed 257
digital DCC can correct the input clock duty error to less than ±1.4%. The resolution of the unit delay cell and the number of delay cells determine the DCC locking range and accuracy. 3 Simulation results The proposed digital DCC circuit was designed in a 0.18 um CMOS technology. The DCC circuit consumes 4.3 mw at 1 GHz and occupies 110 um 80 um. The simulated input and output clock waveforms are shown in Fig. 3 (a) where the duty ratio of each waveform is 40% and 50%, respectively. As shown in Fig. 3 (b) the measured accuracy is within ±1.4% for ±10% input clock duty error over the operation range of 500 MHz to 2 GHz which satisfies the JEDEC standard of ±5% input clock duty error. Fig. 3. Simulation waveform of DCC and measured DCC accuracy over wide frequency range: (a) Simulated output waveform at 1 GHz with 40% input duty ratio, (b) Measured DCC accuracy. 258
4 Conclusion The proposed wide-range DCC keeps a constant output phase even with input clock duty variation and uses the proposed unit delay cell to achieve a wide operation frequency range. Due to digital structure, the DCC circuit does not lose the DCC control information during power-down mode. The DCC circuit can correct duty ratio errors to less than 1.4% and is suitable for use in DDR memories. Acknowledgments This work is financially supported by the Ministry of Education and Human Resources Development (MOE), the Ministry of Commerce, Industry and Energy (MOCIE) and the Ministry of Labor (MOLAB) through the fostering project of the Lab of Excellency. 259