Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery Amit K. Jain, Sameer Shekhar, Yan Z. Li Client Computing Group, Intel Corporation Hillsboro, OR, United States. amit.jain@intel.com; sameer.shekhar@intel.com; yan.z.li@intel.com Abstract The focus of this paper is power integrity design for noise sensitive circuits in the context of integrated voltage regulators (IVRs). Analysis and design require a combination of traditional noise mitigation and power conversion techniques simultaneously accounting for distributed load, parasitics, and decoupling, and IVR control mechanisms. Both passive and active techniques are described to target noise components based on the electrical proximity to their source and the intervening IVR controls. Simulation results are used to illustrate the concepts and effectiveness of design options. passive mitigation options are described in Section V & Section VI, respectively. Section VII includes a summary and concluding remarks. Keywords-integrated votlage regulators, power integrity, self noise, cross noise, feed through noise, PSSR I. INTRODUCTION Integrated voltage regulators (IVR) were introduced in Intel Fourth Generation Core TM products [1-4] for benefits of reduced board power delivery cost and area, fine grain power management for multiple voltage domains, and reduced package size over conventional power delivery architectures [5]. All prior publications have focused on power conversion aspects of IVRs. For example, [6, 7] report IVR inductors designs and efficiency correlations. This paper focusses on power integrity (PI) design for noise sensitive circuits with IVRs. PI solution with IVRs is fundamentally different from traditional PI due to: distributed loads, capacitance, and package routing; switched nature of the power conversion circuit; and active IVR control mechanisms that shape noise from multiple sources in different frequency ranges. While digital computation logic performance is primarily susceptible to minimum voltage [8], analog circuits like phase locked loops (PLLs), clock distribution, and data interface buffers have more varied effects. For example, jitter sensitivity to power supply noise may be higher for external noise sources compared to that for voltage noise generated by circuit itself, and may have frequency bands of high and low sensitivity. PI design with IVR for such loads requires a combination of traditional PI mitigations and utilization of IVR active control mechanisms to achieve optimal solutions. This paper first delineates the components of noise at loads, analyzes the effect of IVR on these components, and then describes active and passive noise mitigation methods that may be needed to meet noise targets. Simulation results for representative power domains are used for illustration. Section II presents a brief overview of IVRs and their PI implications. Section III and IV analyze the noise components and their dependence on IVR design. Active and Figure 1. Integrated voltage regulator based power delivery. Figure 2. Power integrity noise components in an IVR based microprocessor system. II. IVR AND ITS POWER INTEGRITY IMPLICATIONS A. IVR Overview A high level view of IVR power delivery is shown in Fig. 1. A common rail (Vccin) provides input voltage from a mother board (VR) to several IVRs on the die. Each IVR generates voltages for a set of loads, e.g., CPU cores, data interfaces, etc. Fig. 2 shows a more detailed electrical view of the IVR power delivery with two IVRs feeding two sets of loads from
a common input voltage. Each IVR has a feedback controlled buck converter consisting of FETs, drivers, pulse width modulation (PWM), control loop compensator, output filter inductor realized as air core inductors on the package, and distributed output filter capacitance separated by parasitics of the package. The input voltage is switched by the PFET and NFET inverter at frequencies greater than 100 [MHz] and then filtered by the inductor and output capacitors. Duty ratio of the switched inverter output is controlled via feedback to regulate the average output voltage. Due to the switched nature of the voltage regulator the inductor current has a ripple component which upon absorption in the output capacitors produces a voltage ripple at the load points. Usually two or more phases of the converter are employed in parallel with phase shifted switching signals. The inductor currents are out of phase and their summation, the composite output current, benefits from ripple cancellation and increase in the effective frequency. B. Power Integrity Implications The buck power converter relies on filtering of a pulsed waveform via the output inductor-capacitor (L-C) filter. Post filtering some residual voltage ripple reaches the loads as a contributor to the noise. The time varying load current interacts with the effective output impedance (commonly called Z f) of the converter and results in voltage noise, referred to as self noise. The L-C filter introduces a dominant pole and the overall impedance is shaped by the feedback control of the converter. Several independent circuits may be powered from a single IVR. In this case load activity on one load results in voltage noise on the entire power plane, and reaches all other loads after filtering through plane parasitics and local decoupling capacitance. This noise component is called cross noise. In a typical implementation several independent IVRs are supplied from a common input coming from a VR on the board for independent power management of different loads. Computation logic intensive loads like the CPU cores are characterized by fast current changes and the IVR attempts to regulate the load voltage by drawing corresponding current from the input power network. This introduces voltage noise on the input of other IVRs and mitigated by their effective power supply rejection ratio (PSSR) reaches circuits at the outputs. This component of the noise is called feed through noise. In summary, the composite noise in an IVR power delivery is given by the following equation: (1) III. SELF NOISE, CROSS NOISE, & VOLTAGE RIPPLE A. Self Noise The self noise is generated by the load current interacting with the output impedance of the controlled converter. In the frequency domain it is given by: where I o is the load current, Z OL is the output impedance of the converter (including the power plane routing) with the control loop open, & Z CL is the output impedance with the control loop closed, and G loop is the loop gain of the converter. The open loop impedance can be obtained similar to that in a standard power integrity analysis by shorting the buck converter inductor to ground on the switch connection side, representing the case when the duty ratio is constant and the average of the switched output is a constant DC. This impedance is characterized by parallel resonance (a dominant pole pair) between the buck converter inductor and the total output capacitance. As evident from (3), the converter loop gain mitigates the impedance up to frequencies where 1+G loop(s) > 1. The key parameter in the control loop design for output impedance mitigation is the unity gain bandwidth (UGB), the frequency below which G loop(s) > 1. Athough the UGB is not strictly the frequency at which 1+G loop(s) > 1, it serves as a good indicator of the effectiveness of the control loop for output impedance mitigation. Fig. 3 shows Z OL, G loop, and Z CL for a representative IVR domain. The dominant pole is located at a few 100 [khz]. The control loop mitigates the low frequency impedance and the closed loop impedance has a dominant pole between 1 and 2 [MHz]. The control loop UGB is 3.1 [MHz] beyond which the closed and open impedances are quite close. The differences at higher frequency arise due to higher order effects that are out of the scope of this paper. Note that UGBs as high as 80 [MHz] have been achieved with IVRs [2] and are not limited to the values used in this paper for illustration. As expected from the closed loop impedance, a step change in the load current generates voltage noise (in Fig. 3) with components at 1.5 [MHz] and 21 [MHz]. Voltage at all the distributed load locations are plotted and the maximum undershoot is 52 [mv]. (2) (3) where v ripple, v self, v cross, and v ft are the IVR ripple, self-noise, cross-noise, and feed through noise components, respectively. Each of these is discussed in more detail in the next two sections.
Figure 4. Aggressor to victim trans-impedance and voltage transfer function; cross noise. Figure 3. Self noise: open and closed loop impedance; transient response. B. Cross Noise In the frequency domain the cross noise can be characterized by (4) where Iagg is the current drawn by a load acting like an aggressor inducing voltage Vcross at a victim load via transimpedance Ztrans. Note that the trans-impedance is computed in the closed loop situation, i.e., with the IVR control loop enabled. The top plot in Fig. 4 shows a typical Ztrans. It is clear that the trans-impedance does reduce due to the control loop gain. However, this is primarily due to the reduction in the output impedance discussed above. The voltage transfer function from the aggressor to victim (lower plot of Fig. 4) does not change significantly due to the IVR control loop due to close electrical proximity of the aggressor and victim loads. Fig. 4 shows the voltage noise at victim loads due to a step change in the aggressor load current. As evident the cross noise droop can be in the 20 [mv] range, a significant contribution if the total noise targets are in the tens of milli-volt. C. Ripple The switched nature of the buck converter adds voltage ripple at the load. The voltage ripple can be reduced by increasing the switching frequency of the IVR or increasing the inductance, both of which increase converter losses. Fig. 5 shows this trade-off and Table I lists the voltage ripple and total inductor loss numbers at one current level to illustrate the trade-off. In this particular design 5 [nh] is an optimal choice beyond which voltage ripple benefits diminish while incremental loss penalty increases. TABLE I. VARIATION OF INDUCTOR LOSS AND WORST CASE VOTLAGE RIPPLE ON A REPRESENTATIVE DISTRIBUTED LOAD. L [nh] Inductor Loss at Io=1[A] [mw] Voltage Ripple [mv] 3 426 56 4 445 38 5 467 27
frequency. Beyond the UGB, the attenuation of input to output noise is provided by the L-C filter. The range of effectiveness of each mechanism can be seen in Fig. 7. There is a minima in the PSSR where the control loop gain is not high enough and L-C filter attenuation is also quite low. At high frequencies the PSSR is a function of the parasitic elements in the PDN. Voltage noise at the victim load due to noise at the aggressor load IVR input is shown in Fig. 7. While the PSSR attenuates the droop from 169 [mv] to 5[mV], a 5 [mv] absolute noise is quite large for sensitive analog circuit loads like PLLs. Figure 5. Trade-off with inductance value: voltage ripple; inductor loss across load current. IV. FEEDTHROUGH NOISE In this section we discuss the mechanism and individual stages by which noise from one IVR output results in noise on the output of other IVRs. Voltage disturbance on the input on one IVR due to load transient at its output is also reflected at the input of other IVRs. This can be characterized by where, G vic,agg(s) is the voltage transfer function from the input of the aggressor load IVR to the input of the victim load IVR. A representative G vic,agg(s) and the transient noise transfer are shown in Fig. 6. Peaks in the transfer function occur at peaks of the input plane impedance looking from all the IVRs to the VR on the board. Thus, one method to attenuate the voltage transfer function is by reduction of the input impedance as a whole. As seen in Fig. 6 a high noise can be expected at the victim load IVR input. Voltage noise at the victim load IVR input is shaped by the PSSR of the IVR. The buck converter PSSR is determined primarily by two mechanisms: the control loop gain, and L-C filter. A typical PSSR plot along with the loop gain and L-C filter voltage transfer function are shown in Fig. 7. The loop gain has high magnitude at low frequencies, so that low frequency changes in input voltage are compensated by the feedback control and not propagated to the output voltage. As expected the control loop provides PSSR only up to the UGB (5) (6) Figure 6. Noise transfer from aggressor input to victim input: voltage transfer function; time domain waveforms. V. ACTIVE MITIGATIONS The previous two sections described the noise mechanisms in IVR power delivery via which different sources contribute to total voltage noise at load circuits. This section will cover active control methods to attenuate self noise, cross noise, and feed through noise. A. IVR Unity Gain Bandwidth As evident in above sections control loop gain and UGB affect three of the four noise components: self noise, cross noise, and feed through noise. Control design therefore maximizes control loop gain and UGB to ensure noise mitigation of the three components. The limits to these are silicon area and power trade-offs for the controller realization and stability margins. The effect of increasing UGB from 3 [MHz] to 5 [MHz] in the example system is shown in Fig. 8. The peak output impedance below 10 [MHz] is reduced by 6.2 [mω] resulting in a self noise reduction of 7.4 [mv]. A proportional
reduction can be expected in the cross noise since the voltage transfer function from aggressor to victim loads on the same IVR output does not change with the control loop. Figure 7. Noise feedthrough for victim: PSSR; Noise at IVR input and feed through to output. The IVR PSSR increases by 4 [db] at its lowest point, due to a corresponding increase in the loop gain at that frequency. As a result the feed through noise component reduces from 4.9 [mv] to 3.6 [mv]. B. PSSR Boosting with Input Voltage Feed Forward Control Among the many existing techniques for increasing PSSR of power converters input voltage feed forward in to the control loop and current mode control are most popular. Input voltage feed forward is explored here. Current mode control has similar effects. Both these techniques reduce the system stability margins and have to be used with appropriate input impedance design [9]. (c) Figure 8. Effect of increased UGB: loop gain, output impedance, and PSSR; self noise; and (c) feed through noise voltages. Input voltage feed forward directly changes the duty ratio of the buck converter when input voltage changes. When the input voltage reduces the duty ratio needs to be increased. This direct change of duty ratio avoids the delays in the control loop formed by the L-C filter and compensator. There are several established ways of implementing the input
feed forward. For the purposes of illustration a simple linear reduction of the duty ratio is used in this paper: where d is the duty ratio generated by the feedback control loop, d FF is the duty ratio after incorporating the input voltage feed forward, k FF is a constant feed forward gain, and Δv in is a filtered version of the input voltage. Fig. 9 shows a quantification of the effect on PSSR and voltage noise. The PSSR increases by more than 6 [db] while the feed through noise reduces by almost 50%. (7) frequency mitigation die capacitance has to be used. Filters with corner frequencies lower than 1 [MHz] are hard to realize due to size of the required components. Other passive noise mitigation techniques based on negatively coupled inductors are described in [10]. Fig. 10 shows the schematic for the example system where the victim loads are isolated by adding an L-C filter that suppresses the cross noise. The inductor would be realized by a package structure and the capacitor by a 1 [µf] 0402 form factor discrete capacitor. The filter reduces the voltage transfer function magnitude and therefore coupling in the frequency range of 10-200 [MHz]. As shown in Fig. 10 the package filter reduces cross noise from 52 [mv] to 22 [mv], a 60% reduction. Figure 9. Effect of input voltage feedforward PSSR; voltage noise. VI. PASSIVE TECHNIQUES As indicated in earlier sections cross noise is only indirectly mitigated via reduction of self noise. In several cases the resulting cross noise is unacceptable, especially for some analog circuits that can tolerate high self noise but have extreme sensitivity to external noise. In such cases passive on-package filtering is the only recourse short of adding a second power conversion stage, possibly a high PSSR linear voltage regulator. Conceptually passive noise mitigation techniques for on package power delivery are limited to use of L C filters where the inductor may be realized as a structure in the package routing while capacitor could be either a discrete capacitor on the package or die capacitors. Due to series inductance discrete capacitors can only be effective below some frequency determined by relative values of the PDN and the discrete capacitors parasitic inductances. For higher (c) Figure 10. Cross noise suppresion via package filter: filter implementation; trans impedance; (c) cross noise.
VII. SUMMARY This paper has analyzed different components of noise reaching analog and digital circuits in IVR power delivery architectures. Four noise components are identified and described with their dependency on IVR active control. Noise due to current drawn by the circuit itself (self noise) depends on the output impedance which can be mitigated by IVR control loop up to the UGB frequency; thus, UGB needs to be maximized while maintaining stability margins. IVR control can mitigate noise transferred between loads on the same output PDN (cross noise) indirectly by reducing the self noise; additional passive filtering could be used to meet stringent noise targets albeit with an increase in latency between power state transitions due to the time required to charge up higher capacitances. Noise can be transferred from output of one IVR to the loads on a different IVR via the common input network. This feed through noise can be mitigated by a combination of higher UGB and PSSR boosting techniques like input voltage feed forward control and current mode control. Voltage ripple generated by the switching nature of the IVR itself can be traded with power loss. The concepts covered in this paper combine traditional power integrity and IVR design to provide solutions for noise sensitive circuits in IVR power delivery with applications to microprocessors, FPGAs, and other complex ICs. These become increasingly important with the trend towards higher data rates that require tighter noise budgets, and more feature integration resulting in wider variety of analog and digital loads clustered on the same voltage or electrically coupled via the IVR input supply. Electronic Components and Technology Conference, May 29-June1, 2001, Orlando, Florida, pp. 118-122. [9] R. D. Middlebrook, Input filter considerations in design and applications of switching regulators, in Proc. IEEE Industry Applications Society Annual Conf., 1976, pp. 366-382. [10] A.K. Jain and S. Shekhar, Novel Power Delivery Noise Mitigation Scheme using Negatively Coupled Inductors, in Proc. 66th IEEE Electronic Components and Technology (ECTC) Conf., Las Vegas, NV, USA, May 31 June 3, 2016, pp. 2335 2340. REFERENCES [1] N. Kurd, et. al., Haswell: A family of IA 22nm processors, in Proc. 2014 IEEE International Solid-State Circuits (ISSCC), San Francisco, CA, USA, Feb. 2014, pp. 112-113. [2] T. A. Burton et al., FIVR Fully integrated voltage regulators on 4th generation Intel Core SoCs, in Proc. 29th Annu. IEEE Appl. Power Electron. Conf. Expo., Fort Worth, TX, USA, Mar. 2014, pp. 432-439. [3] G. Schrom, et. al, Optimal Design of Monolithic Integrated DC-DC Converters, in Proc.2006 IEEE International Conference on IC Design and Technology, pp.1-3, May 2006 [4] G. Schrom et. al., A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors, in Proc. of 22 nd Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Feb. 2007, pp. 727-730. [5] S. Shekhar, A. K. Jain, and N. Winer, Power Delivery Impedance Impact of Power Gating Schemes, in Proc. 20th IEEE Workshop on Power and Signal Integrity, Turin, Italy, May 2016, pp. 1 4. [6] W. J. Lambert et. al., Package Inductors for Intel Fully Integrated Voltage Regulators, IEEE Trans. Compon. Packag. Manuf. Technol., vol. 6, no. 1, pp. 3-11, Jan 2016. [7] K. Bharath and S. Venkataraman, Power Delivery Design and Analysis of 14nm Multicore Server CPUs with Integrated Voltage Regulators, in Proc. 66th IEEE Electronic Components and Technology (ECTC) Conf., pp. 368 373, May 31 - June 3, 2016, Las Vegas, NV. [8] A. Waizman and C. Y. Chung, Package capacitors impact on microprocessor maximum operating frequency, in Proc. 51 st