PX74 Quad Frequency HPLL XO PX74 Features Features Description Applications The PX74 is a quad frequency crystal oscillator, XO, based upon ectron s HPLL high performance phase locked loop frequency multiplier ASIC that combines key digital synthesis techniques with I s proven core analog technology blocks. A standard low frequency crystal provides the reference to the fractionaln synthesizer so that virtually any frequency between 0MHz and 00 MHz can be factory programmed allowing quick turn manufacturing. The PX74 has a bit hardware Frequency Select function that provides one of four conditions: Frequency, Frequency, Frequency 3, or Frequency 4. Industry Standard Package,.0 x 7.0 x.8 mm HPLL High Performance PLL ASIC Typical Jitter 00 fsrms ( khz to 0 MHz) Four Output Frequencies from 0 MHz to 00 MHz Spurious Suppression, 70 dbc Typical. or 3.3 Supply oltage LCMOS, LPECL or LDS Output Configurations Output Enable Compliant to EC RoHS Directive Applications PLL circuits for clock smoothing and frequency translation Description Standard 4 Gigabit Fibre Channel 0 Gigabit Fibre Channel 0GbE LAN / WAN Synchronous Ethernet OC9 Block Diagram SONET / SDH DD COutput Output IITS 300 IITS 34003 IEEE 80.3ae ITUT G.8 ITUT G.709 GR3CORE Issue4 FS[] XTAL LCMOS LPECL LDS FS[0] HPLL Gnd Figure Block Diagram Page of 9
PX74 Quad Frequency HPLL XO Performance Specifications oltage Current Electrical Performance Parameter Test Conditions Symbol Min Typ Max Units 3.3 Option. Option LCMOS LDS LPECL Supply DD.97. I DD Operating Temperature, 3 T OP 40 +8 C Output Enable () IH 0.7 x DD 3.3. 90 99 0 3.3.7 98 08 30 IL 0. Frequency Select (FS[], FS[]) IH 0.7 x DD Nominal Frequency IL 0. LPECL/LDS LCMOS Frequency f N 0 0 Temperature Stability, T A = 40 to +8 C f STAB ±0 ppm Outputs LPECL Output midlevel O DD.4 DD. swing (diff) OD..9 PP LDS Output midlevel O.4..8 swing (diff) OD 300 40 00 m PP LCMOS Output OH 0.9 x DD DD Rise/Fall Time (0/80%), Symmetry,3 LPECL/LDS LCMOS with C L = pf LPECL: DD.3 (diff) LDS:. (diff) LCMOS: DD / 00 0 OL 0. x DD t R/ t f 30. SYM 4 0 % Spurious Suppression 70 dbc Jitter (Performance Option N) khz to 0 MHz фj 000 fsrms Jitter (Performance Option A) khz to 0 MHz фj 00 fsrms ma MHz ps ns ] ] 3] 4] ] ] See Standard Frequencies and Ordering Information (Pg 8). Parameters are tested with production test circuit (See Figure for LCMOS, Figure 3 for LPECL and figure 4 for LDS). Parameters are tested at ambient temperature with test limits guardbanded for specified operating temperature. Measured as the maximum deviation from the best straightline fit, per MIL030. Parameters are described with waveform diagram below (Figure ). Not tested in production, guaranteed by design, verified at qualification. Page of 9
PX74 Quad Frequency HPLL XO Test Circuits & Output Waveform FS() FS() 39 Scope Scope 0k 00 00 0k 0k MD MD Figure LCMOS Production Test Circuit Figure 3 LPECL Production Test Circuit FS() t R t F Scope 80% s 0% 0k 0k On Time Period MD Figure 4 LDS Production Test Circuit Figure Waveform Diagram Absolute Maximum Ratings Parameter Symbol Ratings Unit Power Supply DD 0 to 3.8 Input Current I IN 00 ma Output Current I OUT ma oltage Control Range C 0 to DD Output Enable 0 to DD Storage Temperature T STR to C Soldering Temperature / Duration T PEAK / t P 0 / 40 C / sec Page 3 of 9
PX74 Quad Frequency HPLL XO LPECL Application Diagrams FS() 7 FS() 30 30 3 8 4 40 40 8 8 Figure Single Resistor Termination Scheme Resistor values are typically 0 to 40 ohms for 3.3 operation and 8 to 0 ohms for. operation. Figure 7 Pull Up Pull Down Termination Resistor values are typically for 3.3 operation For. operation, the resistor to ground is ohms and the resistor to supply is 40 ohms There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure, and a pullup/pulldown scheme as shown in Figure 7. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left unterminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 0 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. LDS Application Diagrams FS() FS() Receiver 30 30 00 8 8 Figure 8 LDS to LDS, internal 00Ω Figure 9 LDS to LDS, External 00Ω and AC block ing caps Some LDS structures have an internal 00 ohm resistor on the input and do not need additional components. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left unterminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 0 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Page 4 of 9
PX74 Quad Frequency HPLL XO Typical Characteristics Figure 0 Typical Phase Noise/Jitter Performance INTEGER Mode Page of 9
PX74 Quad Frequency HPLL XO Reliability I qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow simulation. The PX74 family is capable of meeting the following qualification tests: Parameter Environmental Compliance Conditions Mechanical Shock MILSTD883, Method 00 Mechanical ibration MILSTD883, Method 007 Solderability MILSTD883, Method 003 Gross and Fine Leak MILSTD883, Method 04 Resistance to Solvents MILSTD883, Method 0 Moisture Sensitivity Level Handling Precautions IPC/JEDEC JSTD00, MSL Although ESD protection circuitry has been designed into the PX74 proper precautions should be taken when handling and mounting. I employs a human body model (HBM) and a chargeddevice model (CDM) for ESD susceptibility testing and design protection evaluation. ESD Ratings Model Minimum Conditions Human Body Model 000 MILSTD883, Method 30 Charged Device Model 900 JEDEC, JESDC0 Machine Model 00 JEDEC, JESDAA Reflow Profile (IPC/JEDEC JSTD00) Parameter Symbol alue PreHeat Time t S 0 sec Min, 80 sec Max Ramp Up R UP 3 C/sec Max Time Above 7 C t L 0 sec Min, 0 sec Max Time To Peak Temperature T AMBP 480 sec Max Time at 0 C t P 0 sec Min, 40 sec Max Ramp Down R DN C/sec Max The device has been qualified to meet the JEDEC standard for PbFree assembly. The temperatures and time intervals listed are based on the PbFree small body requirements. The temperatures refer to the topside of the package, measured on the package body surface. The PX74 device is hermetically sealed so an aqueous wash is not an issue. Terminal Plating: Electrolytic Ni >.9µm Electrolytic Au > 0.7µm Page of 9
PX74 Quad Frequency HPLL XO Outline & Marking Diagram Suggested Pad Layout FFF3F4 Y = Year WW = Week C = Option Codes FFF3F4 = Frequencies (See Ordering Info) mm [inch] Pin Out Pin Symbol Function No Connect Output Enable 3 GND Case and Electrical Ground 4 Output Output COutput (N/A for LCMOS) Complementary Output (N/C for LCMOS) CC Power Supply oltage 7 FS[] Frequency Select MSB 8 FS[0] Frequency Select LSB :Output Enable is internally pulled to DD with a 30 kω resistor. If option C is selected, must be pulled low by the user with a LCMOS logic device or a 3 kω resistor to ground. : FS and FS0 are internally pulled to DD with a 30 kω resistor Output Enable Option oltage Level Result H Output Enable A L Output Disable H Ouput Disable C L Output Enable Frequency Select FS() Pin 7 Pin 8 Fout 0 0 F 0 F 0 F3 F4 Tape & Reel (EIA48A) Tape Dimensions (mm) Reel Dimensions (mm) Dimension W F Do Po P A B C D N W W # Per Tolerance Typ Typ Typ Typ Typ Typ Min Typ Min Min Typ Max Reel PX74 7.. 4 8 78. 3 0. 0.4.4 00 Page 7 of 9
PX74 Quad Frequency HPLL XO Standard Frequency Table Standard Factory Configurable Frequencies (MHz) 8.700000 EE 39.0000 HH 73.780000 K8 73.370748 ND.080000 P 78.0000 T9 9.000000 DD 39.3000 HD 74.0000 K 73.43700 NP 4.93800 PD 79.87000 TB 9.3980 DX 39.843700 HJ 74.78000 KA 7.8387 NA 4.704800 P 800.000000 TK 9.4400000 D 40.0000000 JF 74.00000 K7 8.0000 N8.000000 P3 80.400 TA 9.300 DZ 40.83030 KK 7.0000000 KH 8.874 NM 7.3900 P7 809.0300 TE 9.08000 DB 40.900000 J 7.8000000 K4 84.000000 NG 9.987800 PA 89.00000 TH 9.98980 DK 4.0888870 KM 77.700000 K 84.30000 NH 37.00000 PG 8.777300 TF 9.790000 DH 4.7440 KP 78.0000000 LH 87.00000 N 40.000000 PN 80.000000 TJ 9.9870 ED 4.00000 LM 78.0000 K3 9.000000 N7 44.30 P4 983.400000 TU 0.0000000 E 4.83930 KT 78.43000 K 00.000000 NE 4.0000 RJ,000.0000 TM 0.4000 E.0000000 JB 79.87000 KG 00.9000 N 47.39400 PE 0.4800000 E4 4.0090 K 80.0000000 K9 0.400 N 47.0800 PK Recent Adds: 0.444340 EF 4.000000 JC 80.430 KJ.00000 NF 49.970300 PF 74.703083 NX 0.73000 E 4.00000 JZ 8.777380 KL 9.497 NL 7.487 PB 7.000000 W 0.8870 EG 44.09440 KX 8.9440000 K 40.000000 NR.00 PC 98.8330 C 0.88000 EB 44.4343000 LF 83.34880 KN 43.000000.48 P 0.940 EH 44.8000 JW 83.80 KR 4.70000 N9 9.800 R.000840 EJ 44.730000 J3 84.003380 KU 0.000000 NT 9.38 R3.0000000 E9 44.980000 JE 8.83740 LJ.748 NJ 9.4900 R.04770 EK 4.84000 JG 88.490880 KW.000000 NK 70.83800 R7.7000 E 4.840000 JM 9.7000000 LK.44000 NB 7.000000 RT.79000 E8 4.037940 LG 97.000000 KE 9.749 NN 7.0 TX 4.0000000 EC 4.700000 JK 00.000000 L8 300.000000 PT 7.7 R 4.70000 E 4.870000 JY 0.000000 L 307.00000 RX 73.400 RA 4.7040000 E7 48.0000000 J 0.0000 L9 3.040000 P 84.400 R9.0000000 F7 49.0000 J7 08.000000 LA 3.00000 PU 87.700000 T.8000 F8 49.4080000 J 0.000000 L 38.70000 P 90.99 R4.000000 F 0.0000000 JD.000000 L 30.000000 PP 93.4870 R.900000 F 0.0480000 KD 4.000000 L3 3.0 PW 93.4899 R.0000000 F3.000000 LL 0.000000 LC 38.7090 PX 93.70000 R8 7.0000000 F4.8400000 J4.880000 LB 333.70 PY 9.390 RW 7.480000 FB.0000000 JP 4.4000 L7 334.3300 RB 9.4478 8.7040000 F 3.3300000 JU.000000 L4 33.0830 RC 9.487 TY 9.49000 F 4.740000 JL 30.000000 LD 33.730 RD 704.38000 TG 9.000000 F9.0000000 JX 3.07000 LN 38.40000 RY 707.3700 TC 30.0000000 HE 0.0000000 JR 39.4000 L 37.000000 RF 707.00000 30.700000 H.3800000 KY 0.000000 M8 38.800000 RU 70.94800 T 30.8800000 HF.4400000 J 0.44000 M 400.000000 RR 7.0000 TW 3.00000 H8.080000 J8 3.00000 MA 409.00000 RE 7.7300 T 3.0000000 H.000000 J9.0000 M 49.0000 PM 78.70000 T 3.780000 H3.94000 LE.0000 M3 00.000000 RK 79.734400 T3 33.0000000 H7 3.300000 JJ 9.37000 M7 0.000000 3 737.80000 TL 33.3330000 HC 3.897000 JN 0.000000 M 3.000000 PH 739.00000 TT 34.380000 H 4.0000000 JT.383 M4 3.0000 P8 74.00000 4 34.00000 HB 4.0000 JH 4.347 M9 8.9800 PJ 748.070900 T 3.840000 HG.30000 J.87 M 9.9400 P9 70.000000 T7 37.00000 H4.0000000 JA 7.334 N 88.000000 RH 78.000000 TN 37.0000 H9 70.0000000 KB 8.04078 N3 9.0000 PL 777.00000 T4 37.000000 HK 70.0000 KC 70.000000 N4 00.000000 PR 779.800 T8 38.8800000 H 7.00000 KF 7.00000 NU 4.400000 RG 780.88000 TD Page 8 of 9
PX74 Quad Frequency HPLL XO Ordering Information PX 74 E C E K A N N FFF3F4 Product Family PX: XO Package 74: x 7 x.8 mm Quad Frequency Input E: 3.3 H:. Output A: LCMOS C: LPECL D: LDS Operating Temperature E: 40 to 8 C Example: PX74ECEKANNPP4PBP F, F, F3, F4 (See Standard Frequency Table Performance Option (Future) N: N/A A: 00 fsrms typical Jitter Future N: N/A Enable/Disable A: Enable High C: Enable Low Stability E: ±0 ppm G: ±30 ppm H: ± 3 ppm K: ± 0 ppm S: ± 00 ppm For Additional Information, Please Contact USA: ectron International 7 Lowell Road Hudson, NH 030 Tel:.888.38.7 Fax:.888.39.838 Europe: ectron International Landstrasse, D7494 Neckarbischofsheim, Germany Tel: +49 (0) 338.4784.7 Fax: +49 (0) 338.4784.30 Asia: 8 Yin Cheng Road(C), nd Floor One Lu Jia Zui Pudong, Shanghai 000, China Tel: +8 94 88 Fax: +8 94 99 Disclaimer ectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Page 9 of 9