DATASHEET HA-517 12MHz, Ultra-Low Noise Precision Operational Amplifiers FN291 Rev 1. The HA-517 operational amplifier features an unparalleled combination of precision DC and wideband high speed characteristics. Utilizing the Intersil D. I. technology and advanced processing techniques, this unique design unites low noise (3.2nV/ Hz) precision instrumentation performance with high speed (35V/µs) wideband capability. This amplifier s impressive list of features include low V OS (3mV), wide gain bandwidth (12MHz), high open loop gain (15V/mV) and high CMRR (12dB). Additionally, this flexible device operates over a wide supply range (±5V to ±2V) while consuming only 1mW of power. Using the HA-517 allows designers to minimize errors while maximizing speed and bandwidth in applications requiring gains greater than ten. This device is ideally suited for low level transducer signal amplifier circuits. Other applications which can utilize the HA-517 s qualities include instrumentation amplifiers, pulse or RF amplifiers, audio preamplifiers and signal conditioning circuits. This device can easily be used as a design enhancement by directly replacing the 725, OP25, OP, OP7, OP27 and OP37 where gains are greater than ten. Features Slew rate..................................... 35V/µs Wide gain bandwidth (A V 1)................. 12MHz Low noise.......................... 3.2nV/ Hz at 1kHz Low V OS........................................ 3µV High CMRR................................... 12dB High gain.................................. 15V/mV Applications High speed signal conditioners Wide bandwidth instrumentation amplifiers Low level transducer amplifiers Fast, low level voltage comparators Highest quality audio preamplifiers Pulse/RF amplifiers For further design ideas see application note AN553 Pin Configuration HA-517 (CERDIP) TOP VIEW BAL 1 8 BAL -IN IN 2 3-7 V OUT V- 5 NC Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # HA7-517-2 HA7-517-2-55 to 125 8 Ld CerDIP F8.3A HA7-517R525 (Note 1) HA7-517R525-55 to 125 8 Ld CerDIP with Pb-free Hot Solder DIP Lead Finish (SnAgCu) F8.3A NOTE: 1. Intersil Pb-free hermetic packaged products employ SnAgCu or Au termination finish, which are RoHS compliant termination finishes and compatible with both SnPb and Pb-free soldering operations. Ceramic dual in-line packaged products (CerDIPs) do contain lead (Pb) in the seal glass and die attach glass materials. However, lead in the glass materials of electronic components are currently exempted per the RoHS directive. Therefore, ceramic dual inline packages with Pb-free termination finish are considered to be RoHS compliant. FN291 Rev 1. Page 1 of 11
Absolute Maximum Ratings T A = 25 C Voltage Between V and V- Terminals........................... V Differential Input Voltage (Note 2)..............................7V Output Current.......................... Full Short-circuit Protection Operating Conditions Temperature Range HA-517-2.................................... -55 C to 125 C Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) CERDIP Package (Note 3).............. 135 5 Maximum Junction Temperature (Hermetic Package)............175 C Maximum Storage Temperature Range............. -5 C to 15 C Maximum Lead Temperature (Soldering 1s)................ 3 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. For differential input voltages greater than.7v, the input current must be limited to 25mA to protect the back-to-back input diodes. 3. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±15V, C L 5pF, R S 1Ω. PARAMETER INPUT CHARACTERISTICS TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS Offset Voltage 25-3 1 µv Full - 7 3 µv Average Offset Voltage Drift Full -. 1.8 µv/ C Bias Current 25-15 8 na Full - 35 15 na Offset Current 25-12 75 na Full - 3 135 na Common Mode Range Full ±1.3 ±11.5 - V Differential Input Resistance (Note ) 25.8 - MΩ Input Noise Voltage (Note 5).1Hz to 1Hz 25 -.9.25 µv P-P Input Noise Voltage Density (Note ) f = 1Hz 25-3.8 8. nv/ Hz f = 1Hz - 3.3.5 nv/ Hz f = 1Hz - 3.2 3.8 nv/ Hz Input Noise Current Density (Note ) f = 1Hz 25-1.7 - pa/ Hz f = 1Hz - 1. - pa/ Hz f = 1Hz -.. pa/ Hz TRANSFER CHARACTERISTICS Minimum Stable Gain 25 1 - - V/V Large Signal Voltage Gain V OUT = ±1V, R L = 2kΩ 25 7 15 - V/mV Full 3 8 - V/mV Common Mode Rejection Ratio V CM = ±1V Full 1 12 - db Gain-bandwidth Product f = 1kHz 25 12 1 - MHz f = 1MHz - 12 - MHz FN291 Rev 1. Page 2 of 11
Electrical Specifications V SUPPLY = ±15V, C L 5pF, R S 1Ω. (Continued) PARAMETER OUTPUT CHARACTERISTICS TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS Output Voltage Swing R L = Ω 25 ±1. ±11.5 - V R L = 2kΩ Full ±11. ±13.5 - V Full Power Bandwidth (Note 7) 25 5 5 - khz Output Resistance Open Loop 25-7 - Ω Output Current 25 1.5 25 - ma TRANSIENT RESPONSE (Note 8) Rise Time 25-22 5 ns Slew Rate V OUT = ±3V 25 28 35 - V/µs Settling Time Note 9 25 - - ns Overshoot 25-2 % POWER SUPPLY CHARACTERISTICS Supply Current 25-3.5 - ma Full - -. ma Power Supply Rejection Ratio V S = ±V to ±18V Full - 1 51 µv/v NOTES:. This parameter value is based upon design calculations. 5. Refer to Typical Performance section starting on page.. The limits for this parameter are established based on lab characterization, and reflect lot-to-lot variation. 7. Full power bandwidth established based on slew rate measurement using: Slew Rate FPBW = --------------------------. 2 V 8. Refer to Test Circuits section on page. PEAK 9. Settling time is specified to.1% of final value for a 1V output step and A V = -1. FN291 Rev 1. Page 3 of 11
Test Circuits and Waveforms IN - 1.8kΩ OUT 5pF 2Ω FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT IN IN OUT OUT Vertical Scale: Input =.5V/DIV Output = 5V/DIV Horizontal Scale: 5ns/DIV FIGURE 2. LARGE SIGNAL RESPONSE Vertical Scale: Input = 1mV/DIV Output = 1mV/DIV Horizontal Scale: 1ns/DIV FIGURE 3. SMALL SIGNAL RESPONSE 15V 5Ω 2N1 5kΩ 2kΩ TO OSCILLOSCOPE 15V V IN 2Ω AUT - 2kΩ -15V 5pF V OUT NOTES: 1. A V = -1. 11. Feedback and summing resistors should be.1% matched. 12. Clipping diodes are optional. HP582-281 recommended. FIGURE. SETTLING TIME TEST CIRCUIT FN291 Rev 1. Page of 11
FN291 Rev 1. Page 5 of 11 Schematic Diagram Q N5 D 8 7 Q N57 R 1 C 7 R 2 Z 58 D 59 D 1 Q N2 R 15 Q P5 Q N12 R Q P37 Q P55 Q N25 D R5 R R 25 R 1 Q P32 Q N19 R 1A Q N3 D 53 Q N2 R 9 1 8 BALANCE Q N51 Q P 27 Q N2A D 22 D 23 Q N2A Q P35 3 2 C Q P3 Q P3A Q N39 Q N1 Q N2 R 8 Q N11 R 1 Q N R 2 Q N7 R 2A C 1 Q N52 D 9 Q N D 5 Q P2 D 1 Q P Q N1A R18 Q N1 C 5 Q N13 C Q N1 Q N8 R 1 Q N15 Q P17 R 7 R 3 Q N9 Q P3 Q N5 R 2 C 2 R 22 Q N7 Q N R 23 R 21 Q P Q P1 R 17 Q P38 Q P2 Q N18 R 19 C 3 Q N5 R 11 Q N29 Q P3 D 33 D 3 Q N2 R 12 OUTPUT R 13 Q P21 HA-517
Application Information V R P 1k 1 8 7 2 3 - NOTE: Tested offset adjustment range is V OS 1mV minimum referred to output. Typical range is ±mv with 5 R P =1kΩ. FIGURE 5. SUGGESTED OFFSET VOLTAGE ADJUSTMENT C S R 1 - R 3 R 1 R 2 - R 2 R 3 C S NOTE: Low resistances are preferred for low noise applications as a 1kΩ resistor has nv/ Hz of thermal noise. Total resistances of greater than 1kΩ on either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will improve stability. FIGURE. SUGGESTED STABILITY CIRCUITS Typical Performance Curves T A = 25 C, V SUPPLY = ±15V, unless otherwise specified. 3 12 V S = ±15V, T A = 25 C 2 1 5 OFFSET VOLTAGE (µv) 1-1 -2-3 - -5 VOLTAGE NOISE (nv/ Hz) 8 2 NOISE VOLTAGE NOISE CURRENT 3 2 1 CURRENT NOISE (pa/ Hz) - - - -2 2 8 1 12 TEMPERATURE ( C) 1 1 1 1k 1k 1k 1M FIGURE 7. TYPICAL OFFSET VOLTAGE vs TEMPERATURE FIGURE 8. NOISE CHARACTERISTICS FN291 Rev 1. Page of 11
Typical Performance Curves T A = 25 C, V SUPPLY = ±15V, unless otherwise specified. (Continued) INPUT NOISE VOLTAGE (µv P-P ).1.12.1.8...2 T A = 25 C CMRR (db) 1 12 8 V S = ±15V T A = 25 C 8 1 12 1 1 18 2 SUPPLY VOLTAGE (±V) FIGURE 9. NOISE vs SUPPLY VOLTAGE 1 1 1k 1k 1k 1M 1M FIGURE 1. CMRR vs FREQUENCY 2 T A = 25 C 12 1 PSRR (db) 8 1 12 GAIN (db) 8 2 PHASE GAIN 9 18 PHASE (DEGREES) 1 1 1k 1k 1k 1M 1 1k 1k 1k 1M 1M 1M FIGURE 11. PSRR vs FREQUENCY FIGURE 12. OPEN LOOP GAIN AND PHASE vs FREQUENCY A VOL (1kV/V) AND V OUT (V) 17 T A = 25 C 1 A 15 VOL 1 13 12 V OUT 11 1 9 8 7 5 2 8 1 LOAD RESISTANCE (kω) SLEW RATE NORMALIZED TO 1 AT 3 o C 1.5 R L = 2k, C L = 5pF, T A = 25 C 1. 1.3 1.2 1.1 1..99.98.97.9.95 - - -2 2 8 1 12 TEMPERATURE ( C) FIGURE 13. A VOL AND V OUT vs LOAD RESISTANCE FIGURE 1. NORMALIZED SLEW RATE vs TEMPERATURE FN291 Rev 1. Page 7 of 11
Typical Performance Curves T A = 25 C, V SUPPLY = ±15V, unless otherwise specified. (Continued) 28 SUPPLY CURRENT (ma) 2.82 2.8 2.78 2.7 2.7 2.72 2.7 V O = V, V S = ±15V OUTPUT VOLTAGE (V P-P ) 2 2 1 12 8 R L = 2k, C L = 5pF, T A = 25 C 2.8-55 25 125 TEMPERATURE ( C) FIGURE 15. SUPPLY CURRENT vs TEMPERATURE.M.8M 1.2M 1.M 2M FIGURE 1. V OUT MAX (UNDISTORTED SINEWAVE OUTPUT) vs FREQUENCY R L = 2k, C L = 5pF, T A = 25 C GAIN (db) 3 2 1 GAIN PHASE 9 18 PHASE (DEGREES) 1k 1k 1k 1M 1M 1M A CL = 25,V/V; E N =.8µV P-P RTI Horizontal Scale = 1s/DIV; Vertical Scale =.2µV/DIV FIGURE 17. CLOSED LOOP GAIN AND PHASE vs FREQUENCY FIGURE 18. PEAK-TO-PEAK NOISE VOLTAGE (.1Hz TO 1Hz) FN291 Rev 1. Page 8 of 11
Die Characteristics DIE DIMENSIONS: 1 mils x 5 mils x 19 mils 25µm x 15µm x 83µm METALLIZATION: Type: Al, 1% Cu Thickness: 1kÅ ±2kÅ SUBSTRATE POTENTIAL (POWERED UP): V- Metallization Mask Layout BAL HA-517 PASSIVATION: Type: Nitride (Si 3 N ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ TRANSISTOR COUNT: 3 PROCESS: Bipolar Dielectric Isolation BAL -IN V IN OUT V- NC FN291 Rev 1. Page 9 of 11
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN291.1 Updated to newest standards and layout. Figure 18 page 8. Changed Vertical Scale =.2µV/Div to: Vertical Scale =.2µV/DIV Added Revision History and About Intersil sections to page 1 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN291 Rev 1. Page 1 of 11
Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (1, N, N/2, and N/21) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y1.5M - 1982. 1. Controlling dimension: INCH E L M c1 ea/2 S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A S ea c D S (c) F8.3A MIL-STD-1835 GDIP1-T8 (D-, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.2-5.8 - b.1.2.3. 2 b1.1.23.3.58 3 b2.5.5 1.1 1.5 - b3.23.5.58 1.1 c.8.18.2. 2 c1.8.15.2.38 3 D -.5-1.29 5 E.22.31 5.59 7.87 5 e.1 BSC 2.5 BSC - ea.3 BSC 7.2 BSC - ea/2.15 BSC 3.81 BSC - L.125.2 3.18 5.8 - Q.15..38 1.52 S1.5 -.13-7 9 o 15 o 9 o 15 o - aaa -.15 -.38 - bbb -.3 -.7 - ccc -.1 -.25 - M -.15 -.38 2, 3 N 8 8 8 Rev. /9 Copyright Intersil Americas LLC 23-215. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN291 Rev 1. Page 11 of 11