FIELD EFFECT TRANSISTORS Module 5
Introduction Symbol Features: 1. Voltage is applied across gate and source terminals. This voltage controls the drain current. Hence FET is a voltage controlled device. 2. Unipolar device: conduction is due to either holes or electrons 3. Less space than BJT, hence preferred in IC 4. Has very high input impedance (one to several Mega Ohms) 5. Turn-on and turn-off speed of a FET is superior compared to BJT. 6. Better frequency response.
Construction and Characteristics of JFET (N-Channel) Major part of the structure is n type material and hence it is an N-CHANNEL FET Top and bottom portion of n-channel is connected to Drain(D) and Source(S) terminals via ohmic contacts. The small two islands of p-layer is connected together to form Gate(G) terminal. Gate to source voltage (VGS) controls the drain current flow. There are two p-n junctions present in the FET. Under no a. N-Channel FET bias condition, two depletion layers are formed at each junction.
Construction and Characteristics of JFET ( P-Channel) Major part of the structure is n type material and hence it is an P-CHANNEL FET Top and bottom portion of n-channel is connected to Drain(D) and Source(S) terminals via ohmic contacts. The small two islands of n-layer is connected together to form Gate(G) terminal. Gate to source voltage (VGS) controls the drain current flow. There are two p-n junctions present in the FET. Under no a. P-Channel FET bias condition, two depletion layers are formed at each junction.
Working of N-Channel When VGS= 0V and VDS>0V, majority charge carriers i.e. electrons start flowing from SOURCE to DRAIN. This constitutes the drain current ID. Notice that, the depletion region is wider near the top of both p-type materials. The reason for this is that the N- channel behaves like a circuit consisting of several series connected resistors. At the top of P-layer, the voltage value will be very high compared to bottom part. This makes the depletion layers to widen up at the top ( due to reverse biasing). As the voltage VDS is increased from OV value, the drain current ID will increase ( Ohmic region) up-to a point called pinch-off. Beyond pinchoff voltage (Vp), ID starts to remain constant (saturation region). If VDS is progressively increased, then beyond a certain point, the p-n junctions break down due to avalanche effect. At this state the device may be permanently damaged.
Characteristics When an external bias voltage say -1V is applied across Gate and Source, the gate channel junctions are further reverse biased, thereby reducing the effective width of channel available for conduction. More the negative voltage across gate and source terminal, deeper would be the penetration of depletion layer and lesser will be the flow of drain current ID.
Characteristics P Channel P - channel JFET is constructed in exactly the same manner as N channel with reversal of P and N materials as shown in the figure. All current directions and voltage polarities are reversed. For VGS = 0V, channel width is maximum. By increasing positive gate to source voltage (VGS), the channel width is reduced.