4-Lines, Uni-directional, Ultra-low Capacitance Transient Voltage Suppressors http//:www.sh-willsemi.com Descriptions The is an ultra-low capacitance TVS (Transient Voltage Suppressor) array designed to protect high speed data interfaces. It has been specifically designed to protect sensitive electronic components which are connected to data and transmission lines from over-stress caused by ESD (Electrostatic Discharge). The incorporates four pairs of ultra-low capacitance steering diodes plus a TVS diode. The may be used to provide ESD protection up to ±2kV (contact discharge) according to IEC6-4-2, and withstand peak pulse current up to 4A (8/2μs) according to IEC6-4-5. The is available in DFN25-L package. Standard products are Pb-free and Halogen-free. Features DFN25-L (Bottom view) 9 GND 8 1 2 3 4 5 I/O1 I/O2 GND I/O3 I/O4 1 2 4 5 3, 8 Pin configuration (Top view) 7 6 Stand-off voltage: 5V max. Transient protection for each line according to IEC6-4-2 (ESD): ±2kV (contact discharge) IEC6-4-4 (EFT): 4A (5/5ns) IEC6-4-5 (surge): 4A (8/2μs) Ultra-low capacitance: C J =.4pF typ. Ultra-low leakage current: I R <1nA typ. Low clamping voltage: V CL = 14V typ. @ = 16A (TLP) Solid-state silicon technology Applications USB 2. and USB 3. HDMI 1.3, HDMI 1.4 and HDMI 2. SATA and esata DVI IEEE 1394 PCI Express Portable Electronics and Notebooks 6V8 * 1 5 6V8 = Device code * = Month code (A~Z) Marking & Pin configuration Order information Device Package Shipping -/TR DFN25-L 3/Tape&Reel 6 Will Semiconductor Ltd. 1 Revision 5., 216/11/2
Absolute maximum ratings Parameter Symbol Rating Unit Peak pulse power (t p = 8/2μs) P pk 48 W Peak pulse current (t p = 8/2μs) 4 A ESD according to IEC6-4-2 air discharge V ESD ESD according to IEC6-4-2 contact discharge ±2 Junction temperature T J 125 Operating temperature T OP -4~85 Lead temperature T L 26 Storage temperature T STG -55~15 ±2 kv Electrical characteristics (T A =25, unless otherwise noted) I V F Forward voltage V RWM Reverse stand-off voltage I F Forward current I R Reverse leakage current V FC Forward clamping voltage V BR Reverse breakdown voltage Peak pulse current V CL Clamping voltage Peak pulse current V FC V F I BR I R V RWM V BR V CL V I F Definitions of electrical characteristics Will Semiconductor Ltd. 2 Revision 5., 216/11/2
Electrical characteristics (T A = 25, unless otherwise noted) Parameter Symbol Condition Min. Typ. Max. Unit Reverse maximum working voltage V RWM 5. V Reverse leakage current I R V RWM = 5V <1 na Reverse breakdown voltage V BR I T = 1mA 7. 8. 9. V Forward voltage V F I T = ma.6.9 1.2 V Clamping voltage 1) V CL = 16A, t p = ns 14 V Dynamic resistance 1) R DYN.35 Ω Clamping voltage 2) V CL V ESD = +8kV 15 V Clamping voltage 3) Junction capacitance V CL C J = 1A, t p = 8/2μs V = 4A, t p = 8/2μs 12 V V R = V, f = 1MHz Any I/O pin to GND.4.65 pf V R = V, f = 1MHz Between any I/O pin.25.4 pf Notes: 1) TLP parameter: Z = 5 Ω, t p = ns, t r = 2ns, averaging window from 6ns to 8ns. R DYN is calculated from 4A to 16A. 2) Contact discharge mode, according to IEC6-4-2. 3) Non-repetitive current pulse, according to IEC6-4-5. Will Semiconductor Ltd. 3 Revision 5., 216/11/2
Typical characteristics (T A = 25, unless otherwise noted) Peak pulse current (%) 9 5 T T 1 Front time: T 1 = 1.25 T = 8 s Time to half-value: T 2 = 2 s T 2 2 Time ( s) 8/2μs waveform per IEC6-4-5 Current (%) 9 3ns t r =.7~1ns Time (ns) 6ns Contact discharge current waveform per IEC6-4-2 t V C - Clamping voltage (V) 12 11 9 Pulse waveform: t p = 8/2 s C J - Junction capacitance (pf).5.45.4.35.3.25 Any I/O pin to GND Between any I/O pin f = 1MHz 8 1 2 3 4 5 - Peak pulse current (A) Clamping voltage vs. Peak pulse current.2 1 2 3 4 5 V R - Reverse voltage (V) Capacitance vs. Reverse voltage Peak pulse power (W) % of Rated power 8 6 4 2 1 1 Pulse time ( s) Non-repetitive peak pulse power vs. Pulse time 25 5 75 125 15 T A - Ambient temperature ( ) Power derating vs. Ambient temperature Will Semiconductor Ltd. 4 Revision 5., 216/11/2
Typical characteristics (T A = 25, unless otherwise noted) ESD clamping (+8kV contact discharge per IEC6-4-2) ESD clamping (-8kV contact discharge per IEC6-4-2) TLP current (A) 2 18 16 14 12 8 6 4 2-2 2 4 6 8 12 14 16 TLP voltage (V) Z = 5 t r = 2ns t p = ns TLP Measurement Will Semiconductor Ltd. 5 Revision 5., 216/11/2
Package outline dimensions DFN25-L.6 Recommend Land Pattern (Unit: mm).5.5 Symbol Dimensions in millimeter Min. Typ. Max. A.5.575.65 A1. -.5 A3.15 Ref. D 2.4 2.5 2.6 E.9 1. 1. D1.3.4.5 E1.3.455.6 b.13.2.25 e.5 BSC L.3.4.5 Notes:.2.2.4 This recommended land pattern is for reference purposes only. Please consult your manufacturing group to ensure your PCB design guidelines are met. Will Semiconductor Ltd. 6 Revision 5., 216/11/2