MagnaChip MC511DB 1.3 Megapixel CMOS Image Sensor 0.18 µm Process Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product, Package, and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan View Analysis 4.3 Pixel Cross-Sectional Analysis 4.4 Color Filters and Microlenses 5 Embedded SRAM Analysis 5.1 SRAM Overview and Cell Schematic 5.2 SRAM Plan View Analysis 5.3 SRAM Cross-Sectional Analysis
Imager Process Review 6 Critical Dimensions 6.1 Die and Bond Pad Dimensions 6.2 Dielectric Thicknesses 6.3 Metallization Critical Dimensions 6.4 Via and Contact Dimensions 6.5 Peripheral MOS Transistor and Poly Dimensions 6.6 STI Isolation 6.7 Well Depths and Die Thicknesses 6.8 Pixel Horizontal Dimensions 6.9 Pixel Vertical Dimensions 6.10 SRAM Transistor Dimensions 7 References 8 Statement of Measurement Uncertainty and Scope Variation Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 LG KU250 Cell Phone Packaging Box Identification Markings 2.1.2 LG KU250 Cell Phone Front View 2.1.3 LG KU250 Cell Phone Back View 2.1.4 LG KU250 Cell Phone Main Board 2.1.5 CIS Assembly Top View 2.1.6 CIS Assembly Tilt View 2.1.7 CIS Assembly Side View 2.1.8 Image Sensor Die Module X-Ray Side View 2.1.9 CIS Assembly Back View 2.1.10 CIS Assembly Open View 2.1.11 CIS on Board Corner Plan View 2.1.12 CIS on Board Corner Tilt View 2.1.13 S5K4BAFX CIS Assembly X-Ray Image Bottom View 2.1.14 MC511DB Die Photograph Color Filters and Microlenses Intact 2.1.15 MC511DB Die Photograph Decapsulated 2.1.16 Die Markings 1 2.1.17 Die Markings 2 2.1.18 NAND (or NOR) Cell 2.1.19 MC511DB Poly Die Photograph 2.1.20 Annotated Die Photograph Analysis Sites 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Die Corner A 2.2.6 Die Corner C 2.2.7 Pixel Array Corner Bottom Left 2.2.8 Pixel Array Corner Delayered to Metal 1 Bottom Left 2.2.9 Pixel Array Corner Top Right 2.2.10 Pixel Array Corner Delayered to Metal 1 Top Right 2.2.11 Microlens Shift Top Left Corner 2.2.12 Microlens Shift Top Right Corner 2.2.13 Microlens Shift Bottom Right Corner 2.2.14 Microlens Shift Bottom Left Corner 2.2.15 Minimum Pitch Bond Pads 2.2.16 Detail of Bond Pad
Overview 1-2 3 Process Analysis 3.1.1 General Structure (P1DS2) 3.1.2 Die Edge Tilt View 3.1.3 Die Edge Structure Detail Tilt View 3.1.4 Die Edge (P1DS2) 3.1.5 Die Edge in Detail (P1DS2) 3.1.6 Die Seal (P1DS2) 3.2.1 Bond Pad Tilt View 3.2.2 Stitch Bond Tilt View 3.2.3 Bond Pad Overview (P1DS2) 3.2.4 Right Bond Pad Edge (P1DS2) 3.3.1 Passivation 3.3.2 Detail of Passivation 1 3.3.3 IMD 3 3.3.4 IMD 2 3.3.5 IMD 1 3.3.6 PMD Periphery 3.4.1 Minimum Pitch Metal 4 3.4.2 Minimum Pitch Metal 3 3.4.3 Metal 3 Composition Detail 3.4.4 Minimum Pitch Metal 2 3.4.5 Minimum Pitch Metal 2 Detail 3.4.6 Metal 2 Composition TEM 3.4.7 Minimum Pitch Metal 1 3.4.8 Metal 1 Composition TEM 3.4.9 Metal 1 Top TEM 3.5.1 Minimum Pitch Via 3s 3.5.2 Minimum Pitch Via 2s and Via 1s 3.5.3 Contacts to Poly 3.5.4 Top of Contact TEM 3.5.5 Minimum Pitch Contacts to Diffusion Si Etch 3.6.1 MOS Transistor Glass Etch 3.6.2 Minimum Polysilicon Pitch Glass Etch 3.6.3 Minimum Gate Length Peripheral NMOS Transistor 3.6.4 Minimum Gate Length Peripheral PMOS Transistor 3.6.5 Minimum Gate Length Pixel NMOS Transistor 3.6.6 Minimum Gate Length Pixel NMOS Transistor TEM 3.7.1 STI 3.7.2 Poly Over STI 3.8.1 SRP of Peripheral N-Well 3.8.2 SRP of Peripheral P-Well 3.8.3 SCM of Peripheral P-Well 3.8.4 SRP of Pixel Array
Overview 1-3 4 Pixel Analysis 4.1.1 MagnaChip MC511DB Pixel Schematic 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Corner Delayered to Metal 1 SEM 4.2.3 Microlenses Plan View (SEM) 4.2.4 Microlenses Tilt View (SEM) 4.2.5 Pixel at Metal 2 4.2.6 Pixel at Metal 1 4.2.7 Pixel at Poly 4.2.8 Pixel at Poly Detail 4.2.9 Pixel at Diffusion Overview 4.2.10 Pixel at Diffusion Detail 4.2.11 SCM of Photocathode 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan View 4.3.2 Transfer Gates T1 and T2 and Pixel Overview (A) 4.3.3 Detail of Transfer Gates T1 and T2 and Pixel (C) 4.3.4 Transfer Gates T1 and T2 (A) 4.3.5 Transfer Gate T2 TEM (A) 4.3.6 Transfer Gate Edge (T1) TEM (A) 4.3.7 Transfer Gate (T1), Gate Oxide Thickness TEM (A) 4.3.8 Silicon Nitride AR Layer (A) 4.3.9 SCM of P-Pinning Layer and Buried Photocathode (A) Overview 4.3.10 SCM of P-Pinning Layer and Buried Photocathode (A) Detail 4.3.11 Reset (T3), Source Follower (T4), and Row Select (T5) Transistor Overview (B) 4.3.12 Detail of Reset Transistor (T3) (D) 4.3.13 Source Follower (T4) and Row Select (T5) Transistor (B) 4.3.14 Reset Transistor (T3) Gate Width (F) 4.3.15 Source Follower Transistor (T4) Gate Width (F) 4.3.16 Row Select Transistor (T5) Gate Width (E) 4.4.1 General Structure of Pixel Through Red and Green Filters TEM 4.4.2 General Structure of Pixel Through Blue and Green Filters SEM 4.4.3 Pixels Near Array Center Angle of Acceptance and Microlens Radius of Curvature (D) 4.4.4 Pixel at Array Edge Right Edge (D) 4.4.5 Pixel at Left Array Edge Dark Pixels (G) 4.4.6 Dark Pixels to Periphery Transition Parallel to Row Select 4.4.7 Edge of Color Filter Array Parallel to Column Out 4.4.8 Organic Lens and Red Color Filter 4.4.9 Organic Lens and Green Color Filter TEM 4.4.10 Red-Green Color Filter Interface TEM 4.4.11 Blue Color Filters
Overview 1-4 5 Embedded SRAM Analysis 5.1.1 Die Photo Showing SRAM Location 5.1.2 SRAM B 5.1.3 6T-SRAM Cell 5.2.1 SRAM at Metal 3 5.2.2 SRAM at Metal 2 5.2.3 SRAM at Metal 1 5.2.4 SRAM at Poly Overview 5.2.5 SRAM at Poly Detail 5.2.6 SRAM at Diffusion 5.3.1 SRAM Cross Section Parallel to Bitline Overview 5.3.2 SRAM Cross Section Through T2/T1 and T4/T3 Gate Width
Overview 1-5 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Cell Phone Identification Markings 2.1.2 Functional Block Sizes 2.2.1 Die and Bond Pad Dimensions 3 Process Analysis 3.3.1 Measured Dielectric Thicknesses 3.4.1 Metallization Thicknesses 3.4.2 Metallization Width and Pitch 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polysilicon Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 3.7.1 STI Critical Dimensions 3.8.1 Well Depths 4 Pixel Analysis 4.2.1 Pixel Horizontal Dimensions 4.4.1 Pixel Vertical Dimensions 4.4.2 Pixel Transistor Dimensions 5 Embedded SRAM Analysis 5.3.1 SRAM Transistor Sizes 6 Critical Dimensions 6.1.1 Die and Bond Pad Dimensions 6.2.1 Measured Dielectric Thicknesses 6.3.1 Metallization Thicknesses 6.3.2 Metallization Width and Pitch 6.4.1 Via and Contact Dimensions 6.5.1 Transistor and Polysilicon Horizontal Dimensions 6.5.2 Transistor and Polysilicon Vertical Dimensions 6.6.1 STI Critical Dimensions 6.7.1 Well Depths 6.8.1 Pixel Horizontal Dimensions 6.9.1 Pixel Vertical Dimensions 6.9.2 Pixel Transistor Physical Dimensions 6.10.1 SRAM Transistor Sizes
About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: 1.613.829.0414 F: 1.613.829.0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com