Features Logic Level Advanced Process Technology Ultra Low On-Resistance 75 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax AUTOMOTIVE MOSFET Description Specifically designed for Automotive applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings I D @ T C = 25 C Parameter Continuous Drain Current, V GS @ V (Silicon Limited) PD - 95848C IRLR295Z IRLU295Z HEXFET Power MOSFET V DSS = 55V R DS(on) = 3.5mΩ I D = 42A HEXFET is a registered trademark of International Rectifier. www.irf.com G D S D-Pak IRLR295Z I-Pak IRLU295Z Units I D @ T C = C Continuous Drain Current, V GS @ V 43 A I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package Limited) 42 I DM Pulsed Drain Current c 24 P D @T C = 25 C Power Dissipation W Linear Derating Factor.72 W/ C V GS Gate-to-Source Voltage ± 6 V E AS (Thermally limited) Single Pulse Avalanche Energyd 57 mj E AS (Tested ) Single Pulse Avalanche Energy Tested Value h 85 I AR Avalanche Currentc See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy g mj T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 3 (.6mm from case ) lbfyin (.Nym) Mounting Torque, 6-32 or M3 screw Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case j.38 R θja Junction-to-Ambient (PCB mount) i 5 C/W R θja Junction-to-Ambient Max. 6 8/28/9
IRLR/U295Z Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 55 V ΔV (BR)DSS /ΔT J Breakdown Voltage Temp. Coefficient.53 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 3.5 mω V GS = V, I D = 36A e 2 mω V GS = 5.V, I D = 3A e 22.5 mω V GS = 4.5V, I D = 5A e V GS(th) Gate Threshold Voltage. 3. V V DS = V GS, I D = 25μA gfs Forward Transconductance 25 S V DS = 25V, I D = 36A I DSS Drain-to-Source Leakage Current 2 μa V DS = 55V, V GS = V 25 V DS = 55V, V GS = V, T J = 25 C I GSS Gate-to-Source Forward Leakage 2 na V GS = 6V Gate-to-Source Reverse Leakage -2 V GS = -6V Q g Total Gate Charge 23 35 I D = 36A Q gs Gate-to-Source Charge 8.5 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 2 V GS = 5.V e t d(on) Turn-On Delay Time 4 V DD = 28V t r Rise Time 3 I D = 36A t d(off) Turn-Off Delay Time 24 ns R G = 5 Ω t f Fall Time 33 V GS = 5.V e L D Internal Drain Inductance 4.5 Between lead, D nh 6mm (.25in.) G L S Internal Source Inductance 7.5 from package and center of die contact S C iss Input Capacitance 57 V GS = V C oss Output Capacitance 23 V DS = 25V C rss Reverse Transfer Capacitance 3 pf ƒ =.MHz C oss Output Capacitance 84 V GS = V, V DS =.V, ƒ =.MHz C oss Output Capacitance 8 V GS = V, V DS = 44V, ƒ =.MHz C oss eff. Effective Output Capacitance 29 V GS = V, V DS = V to 44V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 42 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 24 integral reverse (Body Diode)Ãc V SD Diode Forward Voltage.3 V t rr Reverse Recovery Time 22 33 ns Q rr Reverse Recovery Charge 4 2 nc Conditions V GS = V, I D = 25μA p-n junction diode. T J = 25 C, I S = 36A, V GS = V e T J = 25 C, I F = 36A, V DD = 28V di/dt = A/μs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 www.irf.com
I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLR/U295Z VGS TOP V 9.V 7.V 5.V 4.5V 4.V 3.5V BOTTOM 3.V VGS TOP V 9.V 7.V 5.V 4.5V 4.V 3.5V BOTTOM 3.V 3.V 3.V 6μs PULSE WIDTH Tj = 25 C. V DS, Drain-to-Source Voltage (V) 6μs PULSE WIDTH Tj = 75 C. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics. 6 T J = 25 C. T J = 75 C. V DS = V 6μs PULSE WIDTH. 2. 3. 4. 5. 6. 7. 8. 9.. V GS, Gate-to-Source Voltage (V) Gfs, Forward Transconductance (S) 5 4 3 2 T J = 25 C T J = 75 C V DS = 8.V 38μs PULSE WIDTH 2 3 4 5 I D, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance Vs. Drain Current www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRLR/U295Z 25 2 5 V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss 2 8 I D = 36A V DS = 44V VDS= 28V VDS= V 6 4 5 Coss Crss V DS, Drain-to-Source Voltage (V) 2 2 3 4 5 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage. OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A). T J = 75 C. T J = 25 C. V GS = V..2.6..4.8 2.2 V SD, Source-to-Drain Voltage (V). Tc = 25 C Tj = 75 C Single Pulse μsec msec msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRLR/U295Z 6 5 LIMITED BY PACKAGE 2. I D = 3A V GS = 5.V 4.5 3 2. 25 5 75 25 5 75 T C, Case Temperature ( C).5-6 -4-2 2 4 6 8 2 4 6 8 T J, Junction Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig. Normalized On-Resistance Vs. Temperature D =.5 Thermal Response ( Z thjc )...2..5.2. SINGLE PULSE ( THERMAL RESPONSE ) R R 2 R R 2 τ J τ J τ τ τ 2 τ 2 Ci= τi/ri Ci i/ri. E-6 E-5... t, Rectangular Pulse Duration (sec) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case Ri ( C/W) τi (sec).765.269.64.64 www.irf.com 5 τ C τ
V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRLR/U295Z V DS L 5V DRIVER 24 2 I D TOP 4.3A 6.2A BOTTOM 36A 6 R G 2V V GS tp D.U.T IAS.Ω - V DD A Fig 2a. Unclamped Inductive Test Circuit 2 8 tp V (BR)DSS 4 25 5 75 25 5 75 Starting T J, Junction Temperature ( C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current V Q GS Q GD 3. V G 2.5 Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform 2. I D = 25μA 2V.2μF 5KΩ.3μF.5 V GS D.U.T. V - DS. -75-5 -25 25 5 75 25 5 75 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage Vs. Temperature 6 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) IRLR/U295Z Duty Cycle = Single Pulse..5. Allowed avalanche Current vs avalanche pulsewidth, tav assuming Δ Tj = 25 C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax..E-6.E-5.E-4.E-3.E-2 tav (sec) Fig 5. Typical Avalanche Current Vs.Pulsewidth 6 5 4 3 2 TOP Single Pulse BOTTOM % Duty Cycle I D = 36A 25 5 75 25 5 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ΔT = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avalanche Energy I av = 2DT/ [.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRLR/U295Z - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 7. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Pulse Width µs Duty Factor. % Fig 8a. Switching Time Test Circuit V DS 9% % V GS t d(on) t r t d(off) t f Fig 8b. Switching Time Waveforms 8 www.irf.com
IRLR/U295Z D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.25) 5.2 (.25) 6.73 (.265) 6.35 (.25) - A -.27 (.5).88 (.35) 2.38 (.94) 2.9 (.86).4 (.45).89 (.35).58 (.23).46 (.8) 4.2 (.4).64 (.25).52 (.6).5 (.45) 2X.4 (.45).76 (.3) 2 3 3X 6.22 (.245) 5.97 (.235) - B -.89 (.35).64 (.25).25 (.) M A M B.42 (.4) 9.4 (.37) 6.45 (.245) 5.68 (.224).5 (.2) MIN..58 (.23).46 (.8) LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 2.28 (.9) 4.57 (.8) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX..6 (.6). D-Pak (TO-252AA) Part Marking Information Notes : This part marking information applies to devices produced before 2/26/2 EXAMPLE: THIS IS AN IRFR2 WITH ASSEMBLY LOT CODE 9UP INTERNATIONAL RECTIFIER LOGO IRFU2 6 9U P DATE CODE YEAR = WEEK = 6 ASSEMBLY LOT CODE Notes: This part marking information applies to devices produced after 2/26/2 EXAMPLE: THIS IS AN IRFR2 WITH ASSEMBLY LOT CODE 234 ASSEMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU2 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A www.irf.com 9
IRLR/U295Z I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.25) 5.2 (.25).52 (.6).5 (.45) 6.73 (.265) 6.35 (.25) - A - 4 6.22 (.245) 5.97 (.235).27 (.5).88 (.35) 2.38 (.94) 2.9 (.86).58 (.23).46 (.8) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 2 3 - B - 2.28 (.9).9 (.75) 9.65 (.38) 8.89 (.35) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX..6 (.6). 3X.4 (.45).76 (.3) 2.28 (.9) 2X 3X.89 (.35).64 (.25).25 (.) M A M B.4 (.45).89 (.35).58 (.23).46 (.8) I-Pak (TO-25AA) Part Marking Information Notes : This part marking information applies to devices produced before 2/26/2 EXAMPLE: THIS IS AN IRFR2 WITH ASSEMBLY LOT CODE 9UP INTERNATIONAL RECTIFIER LOGO IRFU2 6 9U P DATE CODE YEAR = WE E K = 6 AS S E MBLY LOT CODE Notes: This part marking information applies to devices produced after 2/26/2 EXAMPLE: THIS IS AN IRFR2 WITH ASSEMBLY LOT CODE 5678 ASS EMBLED ON WW 9, 999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFU2 99A 56 78 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 9 LINE A www.irf.com
IRLR/U295Z D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Limited by T Jmax, starting T J = 25 C, L =.89mH R G = 25Ω, I AS = 36A, V GS =V. Part not recommended for use above this value. ƒ Pulse width.ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. This value determined from sample failure population. % tested to this value in production. When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994 ˆ R θ is measured at T J approximately 9 C Data and specifications subject to change without notice. This product has been designed for the Automotive [Q] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 252-75 TAC Fax: (3) 252-793 Visit us at www.irf.com for sales contact information.8/9 www.irf.com