Qualcomm PM8921 (Die Markings HG11-N1039-300) PMIC Transistor Characterization of N and P-LDMOS Transistor Blocks
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3 Table of Contents Phase 1 Design of Experiment Die Photograph at the Polysilicon Layer P and N-Type LDMOS Transistors of Interest P and N-Type LDMOS Transistors of Interest Detail Measure the LDMOS at the Metal 2 Layer Plan-View SEM Analysis of LDMOS Transistors N-LDMOS at the Metal Layer N-LDMOS at the Metal 2 Layer N-LDMOS at the Metal 1 Layer N-LDMOS at the Polysilicon Layer N-LDMOS at the Polysilicon Layer Detail N-LDMOS Cross Section P-LDMOS Blocks at the Metal 1 Layer P-LDMOS Array Corner at the Polysilicon Layer P-LDMOS Array Corner at the Metal 1 Layer P-LDMOS Array Corner at the Metal 2 Layer P-LDMOS Transistor Pair Cross Section Phase 2 Final Sample Preparation and Measurement Conditions N-LDMOS Sample Preparation N-LDMOS Test Area N-LDMOS IV Measurement Setup: S/D Breakdown, Id - Vg, Id - Vd (3.3 V) Phase 3 Summary of N-LDMOS Electrical Characterization Results N-LDMOS: Source/Drain Reverse Breakdown N-LDMOS: Id - Vg (Vdd = 3.3 V) N-LDMOS: Id - Vd (Vdd = 3.3 V) N-LDMOS IV Measurement Setup: Id - Vg, Id - Vd (Vdd = 6 V) N-LDMOS: IdVg 6 Vdd = V Failed N-LDMOS: Data Log of 6 V Failure N-LDMOS Transistor Characteristics Summary (Vdd = 3.3 V) Phase 2 P-LDMOS Sample Preparation P-LDMOS Test Area P-LDMOS IV Measurement Setup: S/D Breakdown, Id - Vg, Id - Vd (6 V, 9 V, and 12 V) Phase 3 Summary of P-LDMOS Electrical Characterization Results P-LDMOS: Source/Drain Reverse Breakdown P-LDMOS: Id - Vg (Vdd = -3.3 V) P-LDMOS: Id - Vd (Vdd = -3.3 V) P-LDMOS IV Measurement Setup: Id - Vg, Id - Vd (Vdd = -6.00 V) P-LDMOS: Id - Vg (Vdd = -6.0 V) P-LDMOS: Id - Vd (Vdd = -6.0 V) P-LDMOS IV Measurement Setup: Id - Vg, Id - Vd (Vdd = -9.00 V) P-LDMOS: Id - Vg (Vdd = -9.0 V) P-LDMOS: Id - Vd (Vdd = -9.0 V) PMOS IV Measurement Setup: Id - Vg, Id - Vd (Vdd = -12.00 V) P-LDMOS: Id - Vg (Vdd = -12.0 V) P-LDMOS: Id - Vd (Vdd = -12.0 V) P-LDMOS Transistor Characteristics Summary (Vdd = 12 V)
4 Table of Contents Continued Appendix: ICWorks Surveyor Images LDMOS Transistor Blocks ICWorks Surveyor Image N and P-LDMOS at the Metal 5 Layer ICWorks Surveyor Image N and P-LDMOS at the Metal 4 Layer ICWorks Surveyor Image N and P-LDMOS at the Metal 3 Layer ICWorks Surveyor Image N and P-LDMOS at the Metal 2 Layer ICWorks Surveyor Image N and P-LDMOS at the Metal 1 Layer ICWorks Surveyor Image N and P-LDMOS at the Polysilicon Layer ICWorks Surveyor Image N and P-LDMOS at the Polysilicon Layer Detail Statement of Measurement Uncertainty and Scope Variation About Chipworks
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