Advanced High-Density Interconnection Technology Osamu Nakao 1 This report introduces Fujikura s all-polyimide IVH (interstitial Via Hole)-multi-layer circuit boards and device-embedding technology. Employing thin polyimide film as insulation layers, the boards using these technologies feature a very thin structure and excellent reliability. As IVHs connecting adjacent layers are filled with special conductive paste, this allows highdensity wiring, as well as simple fabrication. In addition, the embedding technology enables various 3D arrangements of LSIs and passive components in a multi-layer circuit board. IVHs and embedding technology will enable drastically reduced size of circuit board and the shortest signal path and thus accelerate miniaturization and increase in performance of electronic devices. 1. Introduction Recently, FPCs play a more and more important role for high-density interconnection in mobile electronics. They enable free arrangements of components in limited space, and a low-profile structure because of its thin, bendable body. Owing to the surface smoothness, they have advantages in dense mounting of finepitch LSIs and small components such as FBGA and 0402 passive components. To meet the demand for further functionality in future electronics, we developed a high-density, thin, multilayer FPC, APIC (All-Polyimide IVH Colaminated), and WABE technology (Wafer And Board level Embedding) for embedding low-profile devices in a circuit board. APIC is a multi-layer polyimide circuit board with IVHs in any layer, which allows higher density mounting compared with multi-layer circuit boards of the current technology. WABE is a future wiring technology which will enable a slim structure of circuit board and low transmission losses through three dimensional arrangements of electronic components embedded into multi-layer polyimide circuits. This report describes features and examples of the two technologies mentioned above and the product reliability test results. 2. All-Polyimide IVH Colaminated, APIC 2.1 Structure of APIC An APIC is a multilayer circuit board with laminated insulating polyimide layers connected by IVHs filled with conductive paste. 1)2). PTH(plated through hole) technology is usually used for current multi-layer circuit boards while LVH(laser via hole) technology is 1 : Electron Device Laboratory widely applied to making a micro-via in recent years. Using LVH technology and build-up method in combination largely contributes to the rapid progress of miniaturization and high-density wiring of multi-layer circuit board 3). In the case of a typical LVH, it has been impossible to put a via on another via or put a pad on a via because of dented shape of LVH, in which the side wall and the bottom of laser-drilled hole are conformally copper-plated. However, the latest via-filling technology has overcome such difficulties using special additives to deposit conductor metal selectively in a via hole and to create a flat LVH surface 4). Unrestricted via structure brought by via-filling technology has eliminated dead space and provides the shortest interconnection in multi-layer circuit boards. APIC employs conductive paste for via-filling instead of copper plating. Paste via technology enables skipping complicated via-filling plating processes and avoiding increase in conductor thickness, which is obstructive to make a narrow pitch circuit. Polyimide film used as the insulating base material contributes to the thin structure of APIC. In addition to its mechanical strength, as polyimide shows excellent properties of dielectric and thermal toughness, APIC has great durability and reliability even in harsh environments. The cross sectional structures of APIC, PTH and LVH multilayer circuit boards are shown in Figures 1 (a), (b) and (c). 2.2 Manufacturing Process of APIC APIC employs the colamination method where the lamination of circuit layers is carried out at a time regardless of number of layers. In the colamination method, as patterns of all layers are formed in advance and then pressed by one operation, This can simplify 48
Abbreviations, Acronyms, and Terms. IVH Interstitial Via Hole APIC All-Polyimide IVH Colaminated WABE Technology Wafer And Board level Embedded Technology PTH Plated Through Hole LVH Laser Via Hole FCBGA Flip Chip Ball Grid Array RDL Redistribution Layer (a) PTH multilayer board the manufacturing process of multilayer circuit board. This method is advantageous in shortening the lead times and controlling the quality. The process is shown in Fig. 2. Conductor patterns on each layer are fabricated by the chemical etching of copper foil laminated on polyimide film. The circuit formation process for each layer proceeds in parallel. We can use roll-to-roll machines for efficiently forming circuits. The circuit layers are laminated with adhesive and drilled to make via holes by laser irradiation. After the via holes are filled with conductive paste by screen printing, the circuit layers are aligned and pressed in a vacuum hot press machine. As shown in Fig. 3, the partial multilayer APIC is manufactured by stacking small islands or strips of circuit on the base layer. In the case of the board having small multilayer, material waste can be significantly cut down compared with the conventional method. 2.3 Structural variation of APIC Various structures of APIC are introduced in Fig. 4. Fig. 4 (a) shows the partial multilayer APIC with small circuits on a single-sided base layer. The multilayer board in Fig. 4 (b) has partially separated layers, which are coated with coverlays and gold, and thus enables freedom of bending, connecting and mounting devices (b) LVH multiayer board (c) APIC Fig. 1. Cross sections of PTH multilayer board, LVH multilayer board and APIC. Single sided flex (a) Cross section circuit Single sided flex (b) Schematic illustration of lamination process Fig. 3. Cross sectional structure and lamination process of partial multilayer board. Copper foil Etching Adhesive lamination Polyimide film alignment (a) Partial multilayer APIC Via drilling adhesive Vacuum press (b) APIC with flexes draw out from any-layer Filling of conductive paste Fig. 2. Process flow of APIC. (c) APIC for FCBGA substrate Fig. 4. Structural variation of APIC. Fujikura Technical Review, 2013 49
Table 1. Summary of reliability test results for APIC. item condition result Low temperature humid Temperature cycle humid bias Insulation resistance High voltage durability 125 C, 1000h -40 C 1000h 60 C, 90%RH 1000h -25 125 C 1000cyc 85 C, 85%RH, 30V / 1000h 100V/1min 1000V/1min Insulation resistance>10mω resistance>10 12 Ω (in-plane, between layers) No failure (in-plane, between layers) independently in any layer. The BGA substrate of APIC is shown in Fig. 4 (c). A fine-pitch circuit fabricated by semi-additive process is used for the surface layer. Its minimum line width and spacing have achieved 10 microns and 10 microns respectively. As shown in Fig. 4, APIC is expected to find application to many kinds of future high-density wiring. 2.4 Reliability test results of APIC The typical results of reliability test we performed using 6-layer coupons are summarized in Table 1. The test coupons were pre-treated through three-cycle reflow after soaked at 30 degrees C, 60% Rh for 196 hours. Figures 5(a) and 5(b) show the results of temperature-cycle tests and oil-dip tests on stacked vias in Resistance change (%) 50 40 30 20 10 0 10 20 30 40 50 Temperature cycle test in air 0 1 2 3 4 5 6 7 8 9 10 Temperatute cycle (a) Results of temperature cycle test Oil dip test 1.9 CH1 CH2 CH3 CH4 1.7 1.5 1.3 1.1 0.9 0 128 192 256 320 384 448 512 576 32 64 96 160 224 288 352 416 480 544 Time (sec) (b) Results of oil dip test 10 13 10 12 10 13 10 12 10 11 10 10 10 9 10 8 10 7 L/S 75/75µm L/S 50/50µm 10 11 10 10 10 9 10 8 10 7 Land pitch 300µm Land pitch 300µm 10 6 0 100 200 300 400 500 600 700 800 900 Time (hours) (c) Results of insulation test between conductors of comb pattern 10 6 0 100 200 300 400 500 600 700 800 900 Time (hours) (d) Results of insulation test between vias Diameter of Via/Land=100µm/250µm Line width/separation=50/50~75/75µm d=300~500µm Between centers of via Fig. 5. Reliability test results of APIC. 50
daisy chain. Figures 5(c) and 5(d) show the results of high-temperature-humid-bias tests on the comb-pattern of copper conductors and vias respectively. Neither visual nor electrical failures were observed in any test coupons under each condition of the reliability tests. 3. WABE Technology for device-embedding 3.1 Features We have developed WABE technology, which is used for embedding devices into a polyimide multilayer board. The interconnection method employed in WABE Technology features the combined use of RDL(redistribution layer) formed on LSI through the wafer level packaging process and the copper circuit of CCL(copper clad laminate). The RDL and the circuit on the board are tightly connected by conductive paste vias. The board using polyimide film has not only flexibility and bend-ability but also a quite slim body. Thinness of the board is a strong point of WABE technology in applying it to the manufacturing of module boards and package substrates. The thickness of LSI-embedded board with four circuit layers is 0.22 mm, while that of passivecomponent-embedded board with five circuit layers is 0.26 mm. Both of these thicknesses are the world s minimum of all the currently reported device-embedded boards. The cross sectional views and dimensions of the boards are shown in Fig. 6 and Table 2 respectively. 3.2 Manufacturing process First, copper electrodes are formed on the surface of an LSI to be embedded through the wafer level packaging process. These electrodes act as via pads in multi-layer stacking. The LSI is thinned to less than 0.1 mm by a grinding machine. In the multilayer stacking process as shown in Fig. 7, the thinned LSI is sandwiched between the circuit boards. Via holes are drilled in the board and are filled with raw conductive paste. A cavity is formed in the inner circuit board for putting LSI in it. Passive components are put into the circuit board in the same manner. The stacked board is pressed in a vacuum hot press machine. In the hot press stage, joining of adjacent layers, burying LSI and connecting LSI to circuit board are achieved. A deviceembedded board by WABE Technology has similar structural variations as APIC. Typical embeddable active and passive devices are LSIs with sides ranging from 0.7 mm to 8 mm and passive components of up to 0.15 mm thick. Wafer level packaging Circuit formation WLP Surface layer Inner layer Spacer Bottom layer Alignment Lamination Paste Sintering 500µm (a) LSI-embedded multilayer board (4-layer) Press Embedding Chip Sealing Layers Joining Fig. 7. Process flow of WABE technology. 500µm (b) LSI-and-passive- components-embedded multilayer board (5-layer) Fig. 6. Cross section of device embedded multilayer board. Table 2. Dimensions of device embedded multilayer board employing WABE technology. Wafer level redistribution layer Board level conductor pattern Thickness items Line width separation IC pad pitch Line width separation Via pitch WABE board die dimensions 10 μm 10 μm 80 μm 40 μm 40 μm 300 μm 220 μm 85 μm Table 3. Summary of test results for device-embeddedmultilayer board. item conditions result Low temperature humid Temperature cycle humid bias Autoclave 150 C, 1000h -40 C 1000h 85 C, 85%RH 1000h -40 125 C 1000cyc 85 C, 85%RH, 30V / 1000h 130 C 85%Rh 336h Reflow cycle 250 C peak 10cyc Pre-conditioning : 85 C85%Rh168h(JEDEC MSL1) 250 C peak reflow 3cyc Insulation resistance>10mω Fujikura Technical Review, 2013 51
3.3 Reliability We examined the reliability of test vehicles embedded with a 4 mm square LSI chip. The performance of the product manufactured with WABE technology met the reliability required for a semiconductor package substrate through temperature cycle tests or autoclave after JEDEC level-1 moisture reflow treatment. The test conditions and results are summarized in Table 3. 4. Conclusion This report describes APIC, an advanced multilayer circuit board based on FPC manufacturing and material technologies, and WABE Technology. These unique technologies will provide high density and low profile assembly solution. The reliability of performance of the circuit boards manufactured by these technologies is high enough even for semiconductor package applications. We expect that miniaturization and reduction in restriction of circuit design brought by these technologies will greatly help our customer to create future electronic devices. References 1) O. Nakao, et al.,: IVH Multi-layer Printed Circuit Board Laminated with Polyimide Films, Fujikura Technical Journal, No.103, pp.48-52, 2002 2) T. Hondo, et al.,: The Reliability of All Polyimide Multi Layer Wiring Board, Fujikura Technical Journal, No.116, pp.43-47, 2009 3) A. Murakawa, et al.,: High Density Printed Wiring Board, Fujikura Technical Journal, No.111, pp.31-33, 2006 4) H. Hashiba, et al.,: Multi-layer Buildup Board with Cu Filled Vias, Fujikura Technical Journal, No.108, pp.31-34, 2005 5) M. Okamoto, et al.,: Embedded IC Substrate, Fujikura Technical Journal, No.111, pp.54-58, 2006 6) Y. Sano, et al.,: Thin WLP-IC-Embedded Polyimide Printed Wiring Board, Fujikura Technical Journal, No.119, pp.39-43, 2010 52