EE 570: igital Integrated Circuits and VLI Fundamentals Lec 3: January 18, 2018 MO Fabrication pt. 2: esign Rules and Layout Lecture Outline! MO evice Layout! Inverter Layout! Gate Layout and tick iagrams! esign Rules! tandard Cells! CMO Process Enhancements 2 Big Idea! ystematic construction of any gate from transistors with CMO PUN and PN! Hierarchical design process in three domains (behavioural, structural, and physical) allows for complicated designs motivated cost as a function of performance, yield and design time tatic CMO Gate tructure! rives rail-to-rail " Power rails are V dd and Gnd " output is V dd or Gnd! Input connects to gates # load is capacitive! Once output node is charged doesn t use energy (no static current only leakage)! Output actively driven 3 4 Ideal nmo and pmo Characteristics MOFET N-Type, P-Type G B g = 0 g = 1 g = 1 g = 1! N negative carriers " electrons! witch turned on positive V G! P positive carriers " holes! witch turned on negative V G g G g B a b a g = 0 g = 0 b a g = 1 g = 0 5 V th,n > 0 V G > V th,n to conduct V th,p < 0 V G < V th,p to conduct 6 1
ymmetry ymmetry! NMO: " Electrons are carriers " Electrons flow from source-to-drain " From lowest voltage#highest " rain is most positive terminal " Current flows from drain-tosource! PMO: " Holes are carriers " positively " Holes flow from source#drain " Flow from highest voltage#lowest " rain is most negative terminal " Current flows from source-todrain! ymmetric evice " Like a resistor, doesn t know difference between two ends " rain and source are defined by circuit connections! ymmetric evice " Like a resistor, doesn t know difference between two ends " rain and source are defined by circuit connections 7 8 MO Transistors Typical N-Well CMO Process G B G B 9 10 Typical N-Well CMO Process Interconnect Cross ection 11 ITR 2007 12 2
CMO Layers NMO vs PMO! tandard n-well Process " Active (iffusion) (rain/ource regions)! NMO built on p substrate! PMO built on n substrate " Polysilicon (Gate Terminals) " Needs an N-well " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMO bulk region) " n elect (used with active to create n-type diffusion) " p elect (used with active to create p-type diffusion) 13 14 MO Layout Well, Active, elect MO Layout Well, Active, elect w/ Poly 15 16 Typical N-Well CMO Process CMO Layers! tandard n-well/p-substrate Process " Active (iffusion) (rain/ource regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMO bulk region) " n elect (used with active to create n-type diffusion) " p elect (used with active to create p-type diffusion) 17 18 3
Wiring and Contact Layout ubstrate and Well Contacts! Properties " et Well and ubstrate Voltages to Vdd and Gnd " Prevent Forward Biasing and Latch-Up G " Must Be at Least One per Well " hould Be Placed Regularly B iffusion (Active) Contact Poly Contact Via (metal1-metal2) 19 20 Layout Example: CMO Inverter Layout Example: CMO Inverter! et Pitch (place well and power/ground busses)! Add Transistors (active, select and poly) 21 22 Layout Example: CMO Inverter Layout Example: CMO Inverter! Make Connections (poly, metal, and contacts)! Add ubstrate and Well Contacts 23 24 4
Layout Example: CMO Inverter Example: Mystery Gate! Add External Wiring and Resize 25 26 Example: NAN Gate Example: NAN Gate (Horizontal) 27 28 Layout Example ymbolic Layout! How many transistors?! tick diagrams capture spatial relationships, but abstract away design rules (coming up next )! What are the relative sizes?! How are they connected?! What function does this gate perform? " How many NMO? PMO? / connections? 29 30 5
Layout esign Rules esign Rules! Physical Layer " esign Rules are a set of process-specific geometric rules for preparing layout artwork to enable the layout to be manufacturable, i.e. preserve all of the circuit structures and feature geometries intended by the chip designers! Purpose " Realize fabricated chips that are die area efficient and manufacturable by balancing the conflicting objectives to minimize die area and maximize yield! esign Rule Waiver " Explicit permission granted by the fabrication organization to the design organization to violate certain design rules or to allow certain design rule errors on a given design! Minimum eparation [A] " Intralayer (all layers) " Interlayer (active to poly/well/select) " From Transistor! Minimum Width (all layers) [B]! Minimum Overlap [C] " Past Transistor (poly, active) " Around Contact Cut (all contacted layers) " Around Active (well, select)! Exact ize (contact cuts) [] 31 32 calable CMO Rules Width/pacing esign Rules! efinition " esign Rules Based on a Unitless Parameter (λ) " λ cales with Process Feature ize N-Well Rules Active Rules Poly Rules " λ = 0.5*L min " Example: λ = 0.6um in a 1.2um Process! Advantages " implifies esign - Requires Learning Only One et of esign Rules " Facilitates Translating esigns between Processes Metal Rules 33 34 Contact esign Rules Potential Consequences of esign Rule Violations! Inter-Layer esign Rule Origins Intended Transistor Catastrophic Error Unintended misalignment cause ource-rain short circuit Intended Unrelated Poly & iffusion Catastrophic Error Unintended overlap cause fabrication of a parasitic Transistor 35 36 6
Potential Consequences of esign Rule Violations esign Capture Tools! Inter-Layer esign Rule Origins Both Metal 1 & iffusion Intended Contact Alignment Contact and Via Masks M1 contact to n-diffusion M1 contact to p-diffusion M1 contact to poly Mn contact to Mn-1 for n = 2, 3,.. -> Contact Mask -> Via Mask Both Metal 1 & iffusion Mask misalignment Error Unintended misalignment cause poor contact! Hardware escription Languages (HL) & " capture a textual hierarchical description of design at abstraction ranging from gate or even transistor level up to a behavioral description (eg. VHL, Verilog)! chematic capture " capture a structural, hierarchical graphical representation of the design netlist (eg. Cadence Composer)! Layout " capture a hierarchical view of the physical geometric aspect of a design. The units of hierarchy are called cells, and have physical extent (size). In general, good design requires that only one cell contain the design info for a particular area of the chip (eg. Cadence Virtuoso) 37 38 Testing/Verification Rules Checking! Formal verification is used to show that the design satisfies a formal description of what it should do! imulation is used to show that the design is functional on some well selected set of input vectors! Timing analysis is used to predict design performance! Complex designs invariably suffer design and design entry errors. There are a number of tools and methodologies to detect and correct " Physical esign Rules Checking (RC) checks for design rule violations such as minimum spacing etc. RC checking is complicated by hierarchy and overlap between cells " Electrical Rule Checking (ERC) checks for violations such as shorts between Vdd and GN, opens, and so on " Layout vs. chematic (LV) checks for a one-to-one correspondence between transistor schematic and the layout 39 40 RC Error Example Circuit Extraction! Circuit extraction extracts a schematic representation of a layout, including transistors, wires, and possibly wire and device resistance and capacitance.! Circuit extraction is used for LV, and for spice simulation of layouts 41 42 7
Circuit Extraction Circuit Extraction 43 Example: NAN Gate (Horizontal) 44 tandard Cells! Lay out gates so that heights match " "! Motivation: automated place and route " 45 tandard Cell Area Rows of adjacent cells tandardized sizes EA tools convert HL to layout 46 tandard Cell Layout Example All cells uniform height inv nand3 Cell area Width of channel determined by routing http://www.laytools.com/images/tandardcells.jpg 47 48 8
CMO Process Enhancements Interconnect Cross ection! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias 49 ITR 2007 50 Local Interconnect CMO Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs ITR 2007 51 52 CMO Poly-Poly Capacitors Resistors W L 53 54 9
CMO Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! evices " Multiple thresholds (High and low V t ) " High-k gate dielectrics " FinFET High-K dielectric io 2 ielectric Poly gate MOFET ielectric constant=3.9 High-K ielectric Metal gate MOFET ielectric constant=20 55 56 High-K dielectric urvey 22nm 3 FinFET Transistor Wong/IBM J. of R&, V46N2/3P133 168, 2002 57 High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-etails_presentation.pdf 58 CMO Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " tacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! evices " Multiple thresholds (High and low V t ) " High-k gate dielectrics " FinFET! ilicon on insulator process (OI) " Fabricate on insulator for high speed/low leakage Big Idea! Layouts are physical realization of circuit " Geometry tradeoff " Can decrease spacing at the cost of yield " esign rules! Can go from circuit to layout or layout to circuit by inspection! Can draw stick diagram for any logic gate to help plan layout 59 60 10
Admin! HW 1 due tonight! HW 2 due next week 1/25 " Posted tonight after class 61 11