MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Power Module> TYPE TYPE PS2869 INTEGRTED POWER FUNCTIONS 600/50 low-loss CSTBT inverter bridge for 3 phase DC-to-C power conversion INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (U) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (U), Short circuit protection (SC). (Fig.3) Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a U fault (Lower-side supply). Input interface : 5 line CMOS/TTL compatible. (High ctive) UL pproved : Yellow Card No. E80276 PPLICTION C00~200 three-phase inverter drive for small power motor control. Fig. PCKGE OUTLINES Dimensions in mm (4.5) (3.) 2-f4.5 ±0.2 (4.65) (3.5) (0.6) (2) 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 20 2 27 2.8 ±0.3 (8.5)(2.4) 28 29 30 27 2.8(=75.6) 3 32 35 34 4 40 8.5 ±0.3 (4.4) (2.5) (7.6) (2.4) 33 Type name, Lot No. 22 23 24 25 0 ±0.3 0 ±0.3 0±0.3 20 ±0.3 67 ±0.3 79 ±0.5 B 26 36 37 38 39 () (0) (4.65) (3.5) Heat sink side.5 ±0.5 3 ±0.5 (6.0) ±0.5 2.4 ±0.5 3.4±0.5 C Heat sink side (2.2) (.5) (0.6) 3.8 ±0.2 (2) 7 ±0.5 (2.9) 2.8 ±0.5 34.9 ±0.5 () (0) (.5) Irregular solder remains 0.5MX.9±0.05 ±0.2.6 ±0.5 Detail : (t=0.7) 3.25MX Irregular solder remains 0.5MX.7 ±0.05 0.8 ±0.2.6 ±0.5 Detail : B (t=0.7).85mx TERMINL CODE. UP 2. P 3. UFB 4. UFS 5. P 6. P 7. FB 8. FS 9. WP 0. P. PC 2. WFB 3. WFS (0~5 ) 4. N 5. NC 6. 7. CFO 8. FO 9. UN 20. N 2. WN 22. P 23. U 24. 25. W 26. N DUMMY TERMINL CODE 27. PC 28. UPG 29. P 30. PC 3. PG 32. U 33. WPG 34. 35. UNG 36. NC 37. NO 38. WNG 39. NG 40. W 4. P Detail : C - : Long terminal type (6.0mm)
Fig. 2 INTERNL FUNCTIONS BLOCK DIGRM (TYPICL PPLICTION EXMPLE) C : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C2 : 0.22~2µF R-category ceramic capacitor for noise filtering. Inrush current limiter circuit P High-side input (PWM) (5 line) (Note,2) Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter Protection circuit (U) Protection circuit (U) Protection circuit (U) Drive circuit Drive circuit Drive circuit CBU CBU+ CBW+ CBW CB+ CB C2 C (Note 6) C line input Z Z : ZNR (Surge absorber) C : C filter (Ceramic capacitor 2.2~6.5nF) (Note : dditionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). C NC Low-side input (PWM) (5 line) (Note, 2) (Note 4) Fig. 3 N Drive circuit Input signal conditioning Fo logic Protection circuit FO N CFO Fault output (5 line) (Note 3, 5) Control supply Under-oltage protection H-side IGBTS U W L-side IGBTS (5 line) Note: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage. 2: By virtue of integrating an application specific type HIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 8) 3: This output is open collector type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 0kΩ resistance. (see also Fig. 8) 4: The wiring between the power DC link capacitor and the PN terminals should be as short as possible to protect the against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.~0.22µF, high voltage type) is recommended to be mounted close to these PN DC power input pins. 5: Fo output pulse width should be decided by putting external capacitor between CFO and NC terminals. (Example : CFO=22nF tfo=.8ms (Typ.)) 6: High voltage (600 or more) and fast recovery type (less than 00ns) diodes should be used in the bootstrap circuit. NC D M C line output Fig. 3 EXTERNL PRT OF THE PROTECTION CIRCUIT P Drive circuit Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC () H-side IGBTS U W SC Protection Trip Level External protection circuit L-side IGBTS N Shunt Resistor N (Note ) NC C R Drive circuit B Protection circuit C (Note 2) Note: In the recommended external protection circuit, please select the RC time constant in the range.5~2.0. 2: To prevent erroneous protection operation, the wiring of, B, C should be as short as possible. 0 Collector current waveform 2 tw ()
MXIMUM RTINGS (Tj = 25 C, unless otherwise noted) INERTER PRT Ratings CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature pplied between P-N pplied between P-N Tf = 25 C Tf = 25 C, less than ms Tf = 25 C, per chip (Note ) 450 500 600 50 00 70.4 20~+25 Note : The maximum junction temperature rating of the power chips integrated within the is 50 C (@ Tf 00 C) however, to ensure safe operation of the, the average junction temperature should be limited to Tj(ave) 25 C (@ Tf 00 C). W C CONTROL (PROTECTION) PRT Ratings D DB IN FO IFO SC Input voltage Fault output supply voltage Fault output current Current sensing input voltage pplied between P-PC, N-NC pplied between UFB-UFS, FB-FS, WFB-WFS pplied between UP, P, WP-PC, UN, N, WN-NC pplied between FO-NC Sink current at FO terminal pplied between -NC 20 20 0.5~D+0.5 0.5~D+0.5 0.5~D+0.5 TOTL SYSTEM Ratings Self protection supply voltage limit D = 3.5~6.5, Inverter part CC(PROT) Tj = 25 C, non-repetitive, less than 2 (short circuit protection capability) Tf Module case operation temperature (Note 2) C Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, C minute, connection pins to heat-sink plate 400 20~+00 40~+25 2500 C rms Note 2 : Tf MESUREMENT POINT l Board Specification : Dimensions : 00 00 0mm, Finishing : 2s, Warp : 50~00µm Control Terminals Groove 8mm I board 3.5mm P U W N Power Terminals FWDi Chip IGBT Chip Temp. measurement point (inside the I board) Temp. measurement point (inside the I board) Silicon-grease should be applied evenly with a thickness of 00~200µm
THERML RESISTNCE Rth(j-f)Q Rth(j-f)F Junction to case thermal resistance (Note 3) Inverter IGBT part (per /6 module) Inverter FWDi part (per /6 module) Note 3: Grease with good thermal conductivity should be applied evenly with about +00µm~+200µm on the contacting surface of and heat-sink. Min. Typ. Max..42 2.00 C/W C/W ELECTRICL CHRCTERISTICS (Tj = 25 C, unless otherwise noted) INERTER PRT CE(sat) EC ton trr tc(on) toff tc(off) ICES Collector-emitter saturation voltage FWDi forward voltage Switching times Collector-emitter cut-off current D = DB = 5 IC = 50, Tj = 25 C IN = 5 IC = 50, Tj = 25 C Tj = 25 C, IC = 50, IN = 0 CC = 300, D = DB = 5 IC = 50, Tj = 25 C, IN = 0 5 Inductive load (upper-lower arm) CE = CES Tj = 25 C Tj = 25 C Min. Typ. Max. 0.70.50.60.70.30 0.30 0.40 2.00 0.65 2.00 2.0 2.20.90 0.60 2.60 0.90 0 CONTROL (PROTECTION) PRT ID FOH FOL SC(ref) IIN UDBt UDBr UDt UDr tfo th(on) th(off) Circuit current Fault output voltage Short circuit trip level Input current Supply circuit under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage D = DB = 5 IN = 5 D = DB = 5 IN = 0 Total of P-PC, N-NC UFB-UFS, FB-FS, WFB-WFS Total of P-PC, N-NC UFB-UFS, FB-FS, WFB-WFS SC = 0, FO circuit pull-up to 5 with 0kΩ SC =, IFO = Tj = 25 C, D = 5 (Note 4) IN = 5 Trip level Tj 25 C Reset level Trip level Reset level CFO = 22nF (Note 5) pplied between UP, P, WP-PC, UN, N, WN-NC Min. Typ. Max. 5.00 0.40 7.00 0.55 4.9 0.95 0.43 0.48 0.53.0.5 2.0 0.0 2.0 0.5 2.5 0.3 2.5 0.8 3.0.0.8 2. 2.3 2.6 0.8.4 2. Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 85. 5:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tfo depends on the capacitance value of CFO according to the following approximate equation : CFO = 2.2 0-6 tfo [F]. ms
MECHNICL CHRCTERISTICS ND RTINGS Mounting torque Weight Heat-sink flatness Mounting screw : M4 Recommended.8 N m (Note 6) Min. 0.98 50 Typ. 65 Max..47 00 N m g µm Note 6: Measurement point of heat-sink flatness + Measurement location 3mm Heat-sink side + Heat-sink side RECOMMENDED OPERTION CONDITIONS CC D DB D, DB tdead fpwm IO PWIN NC Supply voltage Control supply variation rm shoot-through blocking time PWM input frequency llowable r.m.s. current Minimum input pulse width NC variation pplied between P-N pplied between P-PC, N-NC pplied between UFB-UFS, FB-FS, WFB-WFS For each input signal, Tf 00 C Tf 00 C, Tj 25 C CC = 300, D = 5, fc = 5kHz P.F = 0.8, sinusoidal Tj 25 C, Tf 00 C (Note 7) ON (Note 8) between NC-N (including surge) Note 7 : The allowable r.m.s. current value depends on the actual application conditions. 8:The input pulse width less than PWIN might make no response. Min. Typ. Max. 0 3.5 3.0 2 300 5.0 300 5.0 5.0 5 400 6.5 8.5 23 5.0 / khz rms ns
Fig. 4 THE INTERNL CIRCUIT UFB UFS P HIC CC B IGBT Di P UP IN HO COM S U FB FS P HIC2 CC B IGBT2 Di2 P IN HO COM S WFB WFS P HIC3 CC B IGBT3 Di3 WP IN HO PC COM S W LIC IGBT4 Di4 UOUT N CC IGBT5 Di5 OUT UN N UN N WOUT IGBT6 Di6 WN WN Fo Fo NO NC GND CFO N CFO