MITSUBISHI SEMICONDUCTOR <pplicati Specific Specific Intelligent Power Power Module> PS PS FLT-BSE TYPE TYPE INSULTED TYPE TYPE PS INTEGRTED FUNCTIONS ND FETURES Cverter bridge for 3 phase C-to-DC power cversi. Circuit for dynamic braking of motor regenerative energy. 3-phase IGBT inverter bridge cfigured by the latest 3rd. generati IGBT and diode technology. Inverter output current capability IO (Note ): Type Name PS % load.8 (rms) 5% over load.2 (rms), min (Note ) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO 2 INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS: For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protecti (SC). Bootstrap circuit supply scheme (single drive power supply) and Under voltage protecti (U). For inverter side lower-leg IGBTs : Drive circuit, Short circuit protecti (SC). Ctrol supply circuit under- & over- voltage protecti (O/U). System over temperature protecti (OT). Fault output signaling circuit (FO) and Current limit warning signal output (CL). For Brake circuit IGBT : Drive circuit Warning and Fault signaling : FO : Short circuit protecti for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side ctrol supply abnormality locking (O/U). FO3 : System over-temperature protecti (OT). CL : Warning for inverter current overload cditi For system feedback ctrol : nalogue signal feedback reproducing actual inverter output phase currents (3φ). Input Interface : 5 CMOS/TTL compatible, Schmitt trigger input, and rm-shoot-through interlock protecti. PPLICTION coustic noise-less.kw/c2 class 3 phase inverter and other motor ctrol applicatis PCKGE OUTLINES 4-R2.5 2 34 56 789 2345678922 2223 2 ±.3 24 2 4 2 4 2 2-φ4 2-R4 4.4 5.8 ±.3 9 = 45.72 ±.8 3 32 33 34 35 36 37 38 39 4.2 4 (2.25) 4 5 24 84.2 ± 72 ±.8.6.5 7.6 ±.5 6 Terminals ssignment: CBU+ 2 CBU 3 CB+ 4 CB 5 CBW+ 6 CBW 7 GND 8 NC 9 DH CL FO 2 FO2 3 FO3 4 CU 5 C 6 CW 7 UP 8 P 9 WP 2 UN 2 N 22 WN 23 Br 3 R 32 S 33 T 34 P 35 P2 36 N 37 B 38 U 39 4 W 3.5 LBEL 8.5 2 2.4 ± 27 ± Ctrol Pin top porti details.3 ~.8.8 ±.5 Main terminal top porti details ~.8.35MX 54 ±.5 62 ±.4.5 ±.3 2 ±.5.5.6 (Fig. ) Jan. 2
MITSUBISHI SEMICONDUCTOR <pplicati Specific Intelligent Power Module> PS FLT-BSE TYPE INSULTED TYPE INTERNL FUNCTIONS BLOCK DIGRM C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change depending the type PWM ctrol scheme used in the applied system) C4 ; 2µF R-category ceramic cdenser for noise filtering. CBU CBU+ CB CB+ CBW CBW+ C4,C3 Brake resistor cnecti, Inrush preventi circuit, etc. P2 B P pplicati Specific Intelligent Power Module Protecti Level shifter Circuit Drive Circuit C2 line input R S T U W M Z C N Z : Surge absorber. C : C filter (Ceramic cdenser 2.2~6.5nF) [Note : dditially an appropriate Line-to line surge absorber circuit maybe necessary depending the applicati envirment]. Current sensing circuit Trig signal cditiing Drive Curcuit FO Logic Protecti circuit CUCCW UPPWPUNNWN Br CL FO FO2 FO3 nalogue signal output correspding to Each phase input (PWM) Fault output each phase current (5 line) Note ) (5 line) Note 2) (5 line) Note 3) Ctrol supply fault sense GND DH (5 line) C 2 line output C2 ; 3.3µF or more Note ) To prevent chances of signal oscillati, an RC coupling at each output is recommended. (see also Fig.) Note 2) By virtue of integrating an applicati specific type HIC inside the module, direct coupling to CPU, without any opto or transformer isolati ispossible. (see also Fig.) Note 3) ll these outputs are open collector type. Each signal line should be pulled up to plus side of the 5 power supply with approximately 5.kΩ resistance. (see also Fig.) Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the SIPM against catastrophic high surge voltage. For extra precauti, a small film type snubber capacitor (.~.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins. T.S. C2 (Fig. 2) MXIMUM RTINGS (Tj = 25) INERTER PRT (Including Brake Part) CC Supply voltage pplied between P2-N CC(surge) Supply voltage (surge) pplied between P2-N, Surge-value P or N Each output IGBT collector-emitter static voltage pplied between P-U,, W, Br or U,, W, Br-N P(S) or N(S) Each output IGBT collector-emitter pplied between P-U,, W, Br or U,, W, switching surge voltage Br-N ±IC(±ICP) IC(ICP) IF(IFP) Each output IGBT collector current Brake IGBT collector current Brake diode anode current TC = 25 Note: ( ) means IC peak value CONERTER PRT CONTROL PRT 3φ rectifying circuit cycle at 6Hz, peak value n-repetitive alue for e cycle of surge current 45 5 6 6 ±2 (±4) 2 (4) 2 (4) RRM Repetitive peak reverse voltage 8 Ea IO IFSM I 2 t Recommended C input voltage DC output current Surge (n-repetitive) forward current I 2 t for fusing DH, pplied between DH-GND, CBU+-CBU, DB Supply voltage 2 CB+-CB, CBW+-CBW CIN Input signal voltage pplied between UP P WP UN N WN Br-GND.5 ~ 7.5 FO IFO CL ICL ICO Fault output supply voltage Fault output current Current-limit warning (CL) output voltage CL output current nalogue current signal output current pplied between FO FO2 FO3-GND Sink current of FO FO2 FO3 pplied between CL-GND Sink current of CL Sink current of CU C CW.5 ~ 7 5.5 ~ 7 5 ± 22 25 38 8 2 s m m m Jan. 2
MITSUBISHI SEMICONDUCTOR <pplicati Specific Intelligent Power Module> PS FLT-BSE TYPE INSULTED TYPE TOTL SYSTEM Tj Tstg TC iso Juncti temperature Storage temperature Module case operating temperature Isolati voltage Mounting torque (Note 2) (Fig. 3) 6 Hz sinusoidal C applied between all terminals and the base plate for minute. Mounting screw: M3.5 2 ~ +25 4 ~ +25 2 ~ + 25.78 ~.27 Note 2) The item defines the maximum juncti temperature for the power elements (IGBT/Diode) of the SIPM to ensure safe operati. However, these power elements can endure juncti temperature as high as 5 instantaneously. To make use of this additial temperature allowance, a detailed study of the exact applicati cditis is required and, accordingly, necessary informati is requested to be provided before use. rms kg cm CSE TEMPERTURE MESUREMENT POINT (3mm from the base surface) TC (Fig. 3) THERML RESISTNCE Symbol Rth(j-c)Q Rth(j-c)F Rth(j-c)QB Rth(j-c)FB Rth(j-c)FR Rth(c-f) Item Juncti to case Thermal Resistance Ctact Thermal Resistance Cditi Inverter IGBT (/6) Inverter FWDi (/6) Brake IGBT Brake FWDi Cverter Di (/6) Case to fin, thermal grease applied ( Module) Min. Typ. Max. 7.3 6. 7.3 6. 4.8.53 ELECTRICL CHRCTERISTICS (Tj = 25, DH = 5, DB = 5 unless otherwise noted) Symbol CE(sat) EC CE(sat)Br FBr IRRM FR t tc() toff tc(off) trr Item Cditi Collector-emitter saturati voltage DH = DB = 5, Input = ON, Tj = 25, IC = 2 FWDi forward voltage Tj = 25, IC = 2, Input = OFF Brake IGBT DH = 5, Input = ON, Tj = 25, IC = 2 Collector-emitter saturati voltage Brake diode forward voltage Tj = 25, IF = 2, Input = OFF Cverter diode reverse current R = RRM, Tj = 25 Cverter diode voltage Tj = 25, IF = 5 /2 Bridge inductive load, Input = ON CC Switching times = 3, Ic = 2, Tj = 25 DH = 5, DB = 5 Note : t, toff include delay time of the internal ctrol FWD reverse recovery time circuit Short circuit endurance CC 4, Input = ON (e-shot) (Output, rm, and Load, Tj = 25 start Short Circuit Modes) 3.5 DH = DB 6.5 CC 4, Tj 25, Switching SO Ic < IOL(CL) operati level, Input = ON 3.5 DH = DB 6.5 Min. Typ. Max. 2.9 2.9.3.6.2..35. 3.5 2.9 8.5.5.6.8. No destructi FO output by protecti operati No destructi No protecting operati No FO output m Jan. 2
MITSUBISHI SEMICONDUCTOR <pplicati Specific Intelligent Power Module> PS FLT-BSE TYPE INSULTED TYPE ELECTRICL CHRCTERISTICS (Tj = 25, DH = 5, DB = 5 unless otherwise noted) Symbol IDH th() th(off) Ri fpwm txx tdead tint CO C+(2%) C (2%) CO C+ C C(2%) nalogue signal over all linear variati rch nalogue signal data hold accuracy td(read) ±IOL ICL(H) ICL(L) SC OT OTr UDH UDHr ODH ODHr UDB UDBr td IFO(H) IFO(L) Item Circuit current Input threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency llowable input -pulse width llowable input signal dead time for blocking arm shoot-through Input inter-lock sensing nalogue signal linearity with output current Offset change area vs temperature nalogue signal output voltage limit nalogue signal reading time Current limit warning (CL) operati level Signal output current of Idle CL operati ctive Short circuit over current trip level Over temperature protecti Reset level Reset level Supply circuit under & Reset level over voltage protecti Reset level Filter time Idle Fault output current ctive Cditi Min. Typ. Max. DH = 5, CIN = 5 5 m.8 2.5 2 Integrated between input terminal-dh TC, Tj 25 DH = 5, TC = 2 ~ + (Note 3) Relates to correspding input (Except brake part) TC = 2 ~ + Relates to correspding input (Except brake part) Ic = DH = 5 Ic = IOP(2%) TC = 2 ~ + Ic = IOP(2%) (Fig. 4) DH = 5, TC = 2 ~ + Ic > IOP(2%), DH = 5 (Fig. 4) CO-C±(2%) Correspd to max. 5 data hold period ly, Ic = IOP(2%) (Fig. 5) fter input signal trigger point (Fig. 8) DH =5, TC = 2 ~ + (Note 4) Open collector output Tj = 25 (Fig. 7) (Note 5) DH =5 TC = 2 ~ + Tj 25 Open collector output.87.77 2.97 4. 2.64 3.5.5.55 8. 6.5..5 3. 6. 9 2. 2.5 9.2 7.5..5 (Note 3) : (a) llowable minimum input -pulse width : This item applies to P-side circuit ly. (b) llowable maximum input -pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operati circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates a pulse-by-pulse scheme. (Note5) : The short circuit protecti works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protecti functi is, thus meant primarily to protect the SIPM against short circuit distracti. Therefore, this functi is not recommended to be used for any system load current regulati or any over load ctrol as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulati or over load ctrol operati. In other words, the PWM signals to the SIPM should be shut down, in principle, and not to be restarted before the juncti temperature would recover to normal, as so as a fault is feed back from its FO pin of the SIPM indicating a short circuit situati. 2.2 5.4 3. 5 65 2.27.7 3.37 5. 3 2. 4. 2 5 2.57.47 3.67.7 5 3.6 9.6 2 2.75 3.25 2.5 8.65 2. 2.5 kω khz ns m % µ m µ m RECOMMENDED CONDITIONS CC Supply voltage pplied across P2-N terminals 4 (max.) DH, DB Ctrol supply voltage pplied between DH-GND, CBU+-CBU, CB+-CB, CBW+-CBW 5±.5 DH, DB Supply voltage ripple ± (max.) CIN() CIN(off) fpwm tdead Input voltage Input off voltage PWM Input frequency rm shoot-through blocking time Using applicati circuit Using applicati circuit ~.3 4.8 ~ 5. 2 ~ 2 2.2 (min.) / khz Jan. 2
MITSUBISHI SEMICONDUCTOR <pplicati Specific Intelligent Power Module> PS FLT-BSE TYPE INSULTED TYPE Fig. 4 OUTPUT CURRENT NLOGUE SIGNLING LINERITY Fig. 5 OUTPUT CURRENT NLOGUE SIGNLING DT HOLD DEFINITION 5 C 4 min max C (2%) DH=5 TC= 2~ C C 5 C() 3 2 4 3 2 nalogue output signal data hold range C C+(2%) C+ 2 3 4 rch= CH(5) CH(55)-CH(5) CH(5) CH(55) Note ; Ringing happens around the point where the signal output voltage changes state from analogue to data hold due to test circuit arrangement and instrumentatial trouble. Therefore, the rate of change is measured at a 5 delayed point. Real load current peak value.(%)(ic=io 2) (Fig. 4) Fig. 6 INPUT INTERLOCK OPERTION TIMING CHRT Input signal CIN(p) of each phase upper arm Input signal CIN(n) of each phase lower arm Gate signal o(p) of each phase upper arm (SIPM internal) Gate signal o(n) of each phase upper arm (SIPM internal) Error output FO Note : Input interlock protecti circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in LOW level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and FO signal is outputted. fter an input interlock operati the circuit is latched. The FO is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Fig. 7 TIMING CHRT ND SHORT CIRCUIT PROTECTION OPERTION Input signal CIN of each phase upper arm Short circuit sensing signal S Gate signal o of each phase upper arm(sipm internal) SC delay time Error output FO Note : Short circuit protecti operati. The protecti operates with FO flag and reset a pulse-by-pulse scheme. The protecti by gate shutdown is given ly to the IGBT that senses an overload (excluding the IGBT for the Brake ). Jan. 2
MITSUBISHI SEMICONDUCTOR <pplicati Specific Intelligent Power Module> PS FLT-BSE TYPE INSULTED TYPE Fig. 8 INERTER OUTPUT NLOGUE CURRENT SENSING ND SIGNLING TIMING CHRT CIN (hold) off off N-side IGBT Current N-side FWDi Current IC (S) +ICL ICL C CL Ref off t(hold) Delay time td(read) Fig. 9 STRT-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO resetting sequence (together with the boot-strap charging sequence) is explained in the following graph DC-Bus voltage Ctrol voltage supply Boot-strap voltage N-Side input signal PN DH DB CIN(N) PWM starts a) b) Fig. RECOMMENDED I/O INTERFCE CIRCUIT CPU 5.kΩ R.nF 5 kω R.nF UP,P,WP,UN,N,WN,Br F,F2,F3,CL CU,C,CW GND(Logic) SIPM P-Side input signal CIN(P) Brake input signal FO output signal CIN(Br) FOI a) Boot-strap charging scheme : pply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 2 number of pulses = ~ 5 depending the boot-strap capacitor size) b) FO resetting sequence: pply ON signals to the following input pins : Br Un/n/Wn Up/p/Wp in that order. Jan. 2