.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial and Industrial: 1//1 Single.V power supply One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power coumption via chip deselect Available in -pin, mil plastic SOJ package and -pin, mil TSOP. Description The IDT1V2 is a,19,-bit high-speed Static RAM organized as K x. It is fabricated using IDT s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT1V2 has an output enable pin which operates as fast as, with address access times as fast as 1. All bidirectional inputs and outputs of the IDT1V2 are TTL-compatible and operation is from a single.v supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT1V2 is packaged in a -pin, mil Plastic SOJ and - pin, mil TSOP. Functional Block Diagram A A1 DECODER,19,-BIT MEMORY ARRAY I/O - I/O I/O CONTROL OE CONTROL LOGIC 22 drw 1 2 Integrated Device Technology, Inc. 1 SEPTEMBER 2 DSC-22/
Meg (K x -bit) Commercial and Industrial Temperature Ranges Pin Configuration Pin Configuration A A1 A2 A A I/O I/O 1 I/O 2 I/O A A A A A9 1 2 9 1 11 1 1 1 1 SO-1 2 1 29 2 2 2 2 2 2 22 21 1 2 1 19 SOJ Top View A1 A1 A1 A1 OE I/O I/O I/O I/O A1 A1 A A11 A1 22 drw 2 A A1 A2 A A I/ I/1 I/2 I/ A A A A A9 1 2 9 1 11 1 1 1 1 1 1 19 2 21 22 SO-2 2 1 9 2 1 29 2 2 2 2 2 2 A1 A1 A1 A1 OE I/ I/ I/ I/ A1 A1 A A11 A1 TSOP Top View 22 drw 11 Pin Description A A1 Address Inputs Input Chip Select Input Write Enable Input OE Output Enable Input I/O - I/O Data Input/Output I/O.V Power Power Ground Gnd 22 tbl 2 Capacitance (TA = +2 C, f = 1.MHz, SOJ package) Symbol Parameter (1) Conditio Max. Unit CIN Input Capacitance VIN = dv pf CI/O I/O Capacitance VOUT = dv pf Truth Table (1,2) 22 tbl NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. OE I/O Function L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) VHC () X X High-Z Deselected - Standby (ISB1) 1. H = VIH, L = VIL, x = Don't care. 2. VLC =.2V, VHC = -.2V.. Other inputs VHC or VLC. 22 tbl 1.2 2
Meg (K x -bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings (1) Symbol Rating Value Unit Recommended Operating Temperature and Supply Voltage VIN, VOUT Supply Voltage Relative to Terminal Voltage Relative to -. to +. V -. to +. V Grade Temperature Commercial C to + C V See Below Industrial C to + C V See Below 22 tbl TBIAS Temperature Under Bias - to + o C TSTG Storage Temperature - to + o C PT Power Dissipation 1 W IOUT DC Output Current ma 22 tbl NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit Supply Voltage... V Ground V VIH Input High Voltage 2. +. (1) V VIL Input Low Voltage -. (2). V 1. VIH (max.) = +2V for pulse width less than, once per cycle. 2. VIL (min.) = 2V for pulse width less than, once per cycle. 22 tbl DC Electrical Characteristics ( = Min. to Max., Commercial and Industrial Temperature Ranges) IDT1V2 Symbol Parameter Test Condition ILI Input Leakage Current = Max., VIN = to ILO Output Leakage Current = Max., = VIH, VOUT = to Min. Max. Unit µa µa VOL Output Low Voltage IOL = ma, = Min.. V VOH Output High Voltage IOH = -ma, = Min. 2. V (1, 2, ) DC Electrical Characteristics ( = Min. to Max., VLC =.2V, VHC =.2V) Symbol Parameter 1V2S/L 1 1V2S/L 1V2S/L 1 Com'l. Ind. Com'l. Ind. Com'l. Ind. 22 tbl Unit ICC ISB ISB1 Dynamic Operating Current S 1 1 1 1 1 1 ma < VLC, Outputs Open, = Max., f = fmax () L 1 1 1 1 1 ma Dynamic Standby Power Supply Current S ma > VHC, Outputs Open, = Max., f = fmax () L ma Full Standby Power Supply Current (static) S 2 2 2 2 2 2 ma > VHC, Outputs Open, = Max., f = () L 1 1 1 1 1 ma 1. All values are maximum guaranteed values. 2. All inputs switch between.2v (Low) and -.2V (High).. Power specificatio are preliminary.. fmax = 1/tRC (all address inputs are cycling at fmax); f = mea no address input lines are changing.. Standard power 1 (S1) speed grade only. 22 tbl.2
Meg (K x -bit) Commercial and Industrial Temperature Ranges AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to.v 1. 1.V 1.V See Figure 1, 2 and 22 tbl 9 AC Test Loads +1.V.V I/O Z =Ω Ω pf 22 drw DATAOUT pf* 2Ω Ω 22 drw Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) taa, ta (Typical, ) 2 1 2 1 1 1 1 2 CAPACITAE (pf) 22 drw Figure. Output Capacitive Derating.2
Meg (K x -bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC =.V ± 1%, Commercial and Industrial Temperature Ranges) 1V2S/L1 (2) 1V2S/L 1V2S/L1 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 1 1 taa Address Access Time _ 1 1 ta Chip Select Access Time _ 1 1 tclz (1) Chip Select to Output in Low-Z tchz (1) Chip Deselect to Output in High-Z _ toe Output Enable to Output Valid _ tolz (1) Output Enable to Output in Low-Z tohz (1) Output Disable to Output in High-Z _ toh Output Hold from Address Change tpu (1) Chip Select to Power Up Time tpd (1) Chip Deselect to Power Down Time _ 1 1 WRITE CYCLE twc Write Cycle Time 1 1 taw Address Valid to End of Write 1 tcw Chip Select to End of Write 1 tas Address Set-up Time twp Write Pulse Width 1 twr Write Recovery Time tdw Data Valid to End of Write tdh Data Hold Time tow (1) Output Active from End of Write twhz (1) Write Enable to Output in High-Z _ 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 2. ºC to +ºC temperature range only for low power 1 (L1) speed grade. 22 tbl 1.2
Meg (K x -bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1 (1) taa trc OE toe DATAOUT tolz () ta tclz HIGH IMPEDAE tchz tohz DATAOUT VALID VCC SUPPLY CURRENT ICC ISB tpu tpd 22 drw (1, 2, ) Timing Waveform of Read Cycle No. 2 trc toh taa toh DATAOUT PREVIOUS DATAOUT VALID DATAOUT VALID 22 drw 1. is HIGH for Read Cycle. 2. Device is continuously selected, is LOW.. Address must be valid prior to or coincident with the later of traition LOW; otherwise taa is the limiting parameter.. OE is LOW.. Traition is measured ±2mV from steady state..2
Meg (K x -bit) Commercial and Industrial Temperature Ranges (1, 2, ) Timing Waveform of Write Cycle No. 1 ( Controlled Timing) taw twc tas (2) twp twr twhz tow tchz DATAOUT () HIGH IMPEDAE () tdw tdh DATAIN DATAIN VALID 22 drw (1, ) Timing Waveform of Write Cycle No. 2 ( Controlled Timing) twc taw tas tcw twr tdw tdh DATAIN DATAIN VALID 22 drw 9 1. A write occurs during the overlap of a LOW and a LOW. 2. OE is continuously HIGH. During a controlled write cycle with OE LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp.. During this period, I/O pi are in the output state, and input signals must not be applied.. If the LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high impedance state. must be active during the tcw write period.. Traition is measured ±2mV from steady state..2
Meg (K x -bit) Commercial and Industrial Temperature Ranges Ordering Information.2
Meg (K x -bit) Commercial and Industrial Temperature Ranges Datasheet Document History /1/99 Updated to new format Pg. 2 Removed SO-1 from TSOP pinout Pg. Revised footnotes on Write Cycle No. 1 diagram Removed footnote for twr on Write Cycle No. 2 diagram Pg. 9 Added Datasheet Document History /1/99 Pg. 1 9 Added Industrial temperature range offerings 11/22/2 Pg. Added die revision option to ordering information /1/ Pg. Updated note, L1 speed grade commercial temperature only and updated die stepping from YF to Y. /2/ Pg. Increased ISB for all "L" and S1 speeds by 1mA and increased for S speed by ma (refer to PCN# SR-2-2). Pg. Added "Restricted hazardous substance device" to the ordering information. 9/2/ Pg. 1, Added Y and V step part numbers to front page and ordering information. Updated the ordering information by removing the IDT notation. CORPORATE HEADQUARTERS for SALES: for Tech Support: 2 Silver Creek Valley Road --1 or ipchelp@idt.com San Jose, CA 91-2-2 --1 fax: -2-2 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc..2 9