Hittite Journl of Science nd Engineering, 2018, 5 (1) 25-29 ISSN NUMBER: 2148-4171 DOI: 10.17350/HJSE19030000074 A New Demodultor For Inverse Pulse Position Modultion Technique Mehmet Sönmez Osmniye Korkut At University, Deprtment Electricl nd Electronics Engineering, Osmniye, TURKEY ABSTRACT Inverse pulse position modultion is one of the modultion techniques for Visile Light Communiction (VLC) systems. In this pper, new demodultor scheme, which is nmed s Slot Period Detector (SPD), is proposed y using frequency detection technique. The proposed rchitecture computes the period time for ech slot. Thnks to SPD technique, the complexity of I-PPM receiver is drmticlly reduced. However, the trditionl receiver hs etter Bit Error Rte (BER) performnce thn tht of proposed SPD structure. The importnt issue is tht whether the proposed receiver is prcticle for rel-time systems hence, the SPD is implemented on Field Progrmmle Gte Arrys (FPGA) ord to demonstrte n pplicle receiver. Article History: Received: 2017/05/05 Accepted: 2017/09/30 Online: 2018/03/28 Correspondence to: Mehmet Sönmez, Osmniye Korkut At University, Deprtment of Electricl nd Electronics Engineering, Osmniye, TURKEY E-Mil: mehmetsonmez@osmniye.edu.tr Keywords: I-PPM, Demodultor, Visile light communiction INTRODUCTION To provide dt trnsmission in indoor communiction systems, Visile Light Communiction (VLC) is promising technique which uses Light Emitted Diode technology. On the contrry wireless RF communiction systems, VLC systems re generlly operted t short distnce due to light power of LED. However, VLC cn serve with different systems since VLC doesn t ffect ny electromgnetic interference compred with RF communiction systems. The receiver side uses photodiode to otin electricl signl from light energy. Therefore, the line of sight is very importnt issue for VLC systems. In order to chieve dt trnsmission in the VLC systems, pulse sed modultion techniques were proposed in the literture. The On-Off Keying (OOK) is the simplest modultion method in the communiction systems. Another modultion technique is the Pulse Position Modultion (PPM) scheme. The PPM scheme hs very dvntge with respect of BER performnce, complexity nd ndwidth efficiency. A new PPM scheme, which is nmed s Vrile Pulse Position Modultion (VPPM), ws proposed to control rightness of LED y using vrile pulse width technique [1]. I-PPM tht is one of the PPM types ws proposed in [2]. This modultion method ws improved y inversing the trditionl PPM technique. Therefore, I-PPM scheme consumes further energy compred with trditionl PPM technique. In [3], the overlpping PPM (OPPM) tht is integrted with trellis coded modultion ws compred with I-PPM nd PPM techniques with respect of dt trnsmission rte. Tht study is theoreticlly nlyzed to performnce of modultion schemes. However, few ppers focused on prcticl design for implementtion of PPM technique. The dimming level is very importnt issue in the V-PPM (Vrile-PPM) scheme. A VPPM trnsmitter rchitecture ws proposed to reduce resource utiliztion of VPPM technique for djustle dimming level [4]. A VPPM demodultor scheme ws designed without knowledge dimming level. The proposed rchitecture ws implemented on rel-time FPGA ord [5]. The demodultor ws improved to provide rpid dimming environment in the pper [6]. The trget dimming level is determined y step-step to ccomplish synchroniztion hence trget dimming level cn t e suddenly otined. In this pper, we propose new PPM demodultor rchitecture to reduce complexity of trditionl PPM receiver. The proposed scheme is sed on period detector. The empty slot is determined y using slot period detector. Additionlly, the demodultor is implemented on rel-time FPGA ord. The dvntges of proposed receiver re explined s follows:
1. In trditionl receiver, the signl genertor is used to multiply received signl. Hence, the signl genertor must e designed for trditionl receiver. However, the proposed rchitecture doesn t consist of signl genertor lock. 2. In order to determine empty slot, decision lock must use the output vlues of integrtors. The input vlues of integrtors re otined t the output of multipliers locks. The multiplier lock must e operted t the trditionl receiver side. There isn t ny multipliction unit in the proposed receiver. I-PPM TECHNIQUE This section gives the trditionl I-PPM trnsmitter nd receiver schemes. I-PPM signl is otined y chnging position of empty slot. The empty slot is situted on pproprite locte considering to dt its condition. In order to generte I-PPM signl, one of the most widely used modultor structures is mux-sed techniques ecuse mux-sed rchitectures opertes using codeword tle. In this scheme, the code tht mtches with the vlue of dt it is ctivted t the output of modultor structure. If i cn e expressed s the deciml equivlent of dt it, n explntion of I-PPM technique cn e written s i i+ 1 0 for t T, T n n IPPM i() t = 2 2 V elsewhere where, T nd n represent one symol period nd it numer in one symol, respectively. The i vlue signifies deciml equivlent of dt it. As shown in the Fig. 1, the loction of empty slot is determined y using deciml equivlent of dt it. Figure 1. I-PPM signl In Fig. 2-, it is shown tht trditionl I-PPM receiver. As shown in the figure, multiplier nd integrtor locks re used to provide correltor-sed receiver system. Moreover, signl genertor locks, which re presented s SG-1, SG- 2, SG-3 nd SG-4, re used to multiply received modulted signl with crrier signl. Firstly, modulted signl is multiplied y crrier signl. Then, the output of multipliction is pplied on integrtor lock which ccumultes to received signl through one symol period. Fig. 2- gives n exmple of signl genertor rchitecture. The counter lock is used (1) Figure 2. The I-PPM receiver,. The trditionl I-PPM receiver,. The signl genertor rchitecture. s common lock for ll SG locks. The Th-2 nd Th-3 re presented s 2T nd 3T in Fig. 1, respectively. For intervl etween 2T nd 3T, the lgorithm provides tht output is eing '0'. PROPOSED SLOT PERIOD DETECTOR SCHEME In this section, we present the proposed demodultor rchitecture which is referred to s slot period detector (SPD). We count high frequency pulse when mplitude of modulted signl is lower thn tht of the threshold vlue which is equl to V/2. The Fig. 3 emphsizes to this sitution. As shown in the Fig. 3, empty slot is filled y high frequency pulses ecuse high frequency pulses nd the output of comprtor lock re pssed through AND gte. If the mplitude of I-PPM signl is higher thn V/2, one of input signls of AND gte is eing 1. This input signl is the output of comprtor lock. Therefore, the output of AND gte is otined squre wve. The proposed receiver cn e expressed s follows: 0 for IPPM => Th e = 1 for IPPM < Th C k T /4 i i= 1 (2) = e (3) where, Th nd e present threshold vlue nd output of comp (comprtor) s shown in Fig. 4. For k {1, 2, 3, 4}, the output of the counter is presented s Ck. The one symol period is expressed s T. As shown in the Eq. (2) nd (3), the counter computes inry '1' level time during 26
proposed seril scheme is suitle for demodultion of I-PPM signl. c Figure 3. I-PPM demodultion process. () I-PPM signl ccording to dt its. () High frequency pulses. (c) AND gte output The Fig. 5 nd Fig. 6 give simultion results of proposed receiver. In the Fig. 5, H.F.P signl is represented s high frequency pulse. The dt, g.dt nd d.dt re defined s input dt, grouped dt nd detected dt, respectively. The dt signl is pplied on input of I-PPM modultor. In order to generte I-PPM signl, dt signl is grouped y two its ecuse the one symol consists of two its. In output of our receiver, the d.dt is otined t the output of decision lock. The modulted I-PPM signl is successfully demodulted t the receiver side ecuse it is shown from the Fig. 5 tht the dt nd d.dt its re sme. The e signl is generted y comprtor lock. According to comprison result of I-PPM signl with threshold vlue, the e signl gets 1 or 0. If threshold vlue is greter thn I-PPM signl, the e signl will e 1 ; otherwise the e signl ecomes logic 0. In the Fig.6, simultion results illustrte BER performnce of the trditionl (T.D.) nd proposed (P.D.) demodultor. Figure 5. Simultion results of the proposed SPD. Figure 4. Proposed I-PPM Structure qurter symol period. Our im is to find the mximum Ck mong C1, C2, C3 nd C4. In experimentl ppliction, the opticl I-PPM signl is converted to electricl I-PPM signl y using photodetector. The electricl I-PPM signl is received y ADC (Anlog to Digitl Converter). The received modulted signl is compred with threshold vlue (Th). This stge determines the structure of received I-PPM signl. The output of comprtor lock (Comp) cts s n enle signl for counter lock. The clock signl of counter lock is H.F.P (High Frequency Pulse) hence the output of counter increses when en nd H.F.P. is logicl '1'. Register (Reg) locks re used to hold sum vlue of counter lock during qurter symol period. The decision lock determines dt its ccording to output of register locks. The filled slot given in the Fig. 3. is determined y decision lock. SIMULATION AND EXPERIMENTAL RESULTS In this section, we give simultion nd experimentl results for proposed demodultor rchitecture. From experimentl nd simultion results, we show tht Figure 6. BER performnce of the receiver rchitectures. As shown in the figure, trditionl demodultor hs etter BER performnce thn tht of proposed demodultor. This is ecuse tht the loction of empty slot is determined y correltion sed receiver. The Fig. 7 gives the receiver rchitecture implemented on FPGA ord. We otin experimentl results y oscilloscope. Firstly, we designed modultor nd demodultor y using FPGA complier. The designed demodultor is shown in the Fig. 7. Then, we operted on rel-time FPGA nd oserved experimentl results on output of the oscilloscope. In Fig. 8 nd Fig. 9, we give 27
Figure 7. The receiver scheme implemented on FPGA ord. Figure 8. Modulted (lue line) nd received (yellow line) signls for low frequency. Figure 9. Modulted (lue line) nd received (yellow line) signls for higher frequency. Figure 11. Modulted signls ccording to dt its. () LSB (Yellow Line) nd I-PPM (Blue Line) signl. () MSB (Yellow Line) nd I-PPM (Blue Line) signl. Figure 10. H.F.P (lue line) nd clock signl of counter (yellow line). Figure 12. Trnsmitted (lue line) nd received (yellow line) dt its. 28
modulted signl (lue line) nd received signl (yellow line). In Fig. 8 nd Fig. 9, dt rte is different hence received signl with higher frequency hs further distortion thn tht of received signl with lower frequency. Fig. 10 shows H.F.P signl (lue line) nd clock signl (yellow line) of counter lock. The output of counter is incresed depending on yellow line signl. In Fig. 11, we give modulted signl ccording to dt its. The Fig. 11 () illustrtes LSB (Lest Significnt Bit) it nd modulted signl while MSB (Most Significnt Bit) nd I-PPM signl re shown in Fig. 11 (). The Fig. 12 shows received (yellow line) nd trnsmitted (lue line) its. As shown the figure, trnsmitted its re successfully estimted t receiver side. References 1. IEEE Stndrd 802.15.7-2011, pp. 1-309, Jun. 2011. 2. Sugiym H, Hruym S, Nkgw M. Experimentl investigtion of modultion method for visile-light communictions. IEICE Trns.Communictions, vol. E89-B (2006) 3393-3400. 3. M X, Lee K, Lee, K. Approprite modultion scheme for visile light communiction systems considering illumintion. Electron. Lett., 48 (2012) 1137 1139. 4. Jeong JD, Lim SK, Jng IS, Kim MS, Kng TG, Chong JW. Novel Architecture for Efficient Implementtion of Dimmle VPPM in VLC Lightings. ETRI Journl, 36 (2014) 905-912. 5. Noh J, Lee S, Kim J, Ju M, Prk Y. A dimming controllle VPPM-sed VLC system nd its implementtion. Optics Communictions 343 (2015) 34-37 6. Lee S, Ahn BG, Ju M, Prk Y. A modified VPPM lgorithm of VLC systems suitle for fst dimming environment. Optics Communictions 365 (2016) 43-48. CONCLUSION In this pper, we propose new receiver to demodulte I-PPM signls. The proposed rchitecture, which is referred to s Slot Period Detector (SPD), hs lower complexity structure thn tht of the trditionl scheme. However, the trditionl scheme gives further BER performnce compred with proposed structure. It cn e shown the difference etween the trditionl nd proposed rchitectures from the Fig. 2 nd the Fig. 4. The proposed scheme is pplied on rel-time FPGA ord. From experimentl nd simultion results, we prove tht the proposed rchitecture is suitle for visile light communiction systems. 29