Current Mirrors Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08
{ Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 { Current Source and Sink Symbol of current source + o deal current source Output resistance - o Practical - characteristics Current sink P Circuit + o N - o N Slope=/ o P MN Current source P + - N Circuit o o N Slope=(-/ o ) MN P P -
Simple Current Mirrors BJT out in Q + - out MN min CE(sat) MOSFET out 0.0 0.36 0.7.08.44.8 = CE in + out min GS - T MN 0.0 0.36 0.7.08.44.8 = DS Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-3 郭泰豪, Analog C Design, 08
ncrease Output esistance of Current Mirrors Using Cascode Structures in out + in out + Q M 4 M Q M 3 M Output impedance BJT: o = r o [+(g m +g o )(r //r o )] r o (+g m r ) MOSFET: o = r ds [+(g m +g mb+ g ds )r ds ] r ds g m r ds Minimum output voltage DC gain of M BJT: min = CE + CE(sat) BE(on) + CE(sat) MOSFET (assume the same size of M -4 same eff ): g4 = gs3 + gs4 = eff + T ; DS = g4 gs = eff + T min = DS(sat) + DS = eff + ( eff + T ) = eff + T Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-4 郭泰豪, Analog C Design, 08
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-5 郭泰豪, Analog C Design, 08 r ds =/λ and L λ For shorter channel lengths, L r ds OPAMP gain Cascode current mirrors can be used to increase output impedance. However, their signal swings are reduced. Wide-swing cascode current mirrors are needed. Example The basic idea is to bias the drain-source voltages of transistors Q and Q 3 to be close to the minimum possible without them going into the triode region. Wide-Swing Current Mirrors bias W / L ( n ) bias Q 5 Q and Q 3 must be biased right at the edge of the triode region. DD in W / L W / L n Q 4 W / L n Q Q 3 Q W / L out = in
Wide-Swing Current Mirrors (Cont.) Let eff be the effective transistor gate-source voltage, GS - th, which is also the minimum DS for a transistor to be biased in the saturation region. Assume all of the transistor drain currents are equal, then eff eff 3 w L n D C (W w L ox L) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-6 郭泰豪, Analog C Design, 08 eff w L ( D DS n w L Cox Since n n n 3 5 L eff eff n 4 eff G G G (n ) eff 5 4 th DS DS G GS G (neff th) 3 5 5 eff out eff eff (n ) eff W L ( w GS 4 DS = eff th ) GS ) DS
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-7 郭泰豪, Analog C Design, 08 Wide-Swing Current Mirrors (Cont.) A common choice: n =, out > eff For a safe design f in = bias, DS should be made a little larger (> eff ), 0.05 to 0. larger depending on transistor - or whether body effect exists. Choose a little larger and f in is a varying current, in bias must be satisfied (i.e. DS = DS3 eff ) W L W L 3
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-8 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit Biasing circuits that provide stable transconductances Transistor transconductances are matched to the conductance of a resistor. As a result, to a first-order effect, the transistor transconductances are independent of power-supply voltage as well as process and temperature variations. 5 Q 0 Q 5 Q 4 Q 00 5 5 5 Example w L w L w L w L w 0 3 L Unity current mirror 4 Q 5 Q 3 B
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-9 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit (Cont.) g eff 3 D3 m3 D5 eff 5 D3 eff 3 D5 B the other current mirror equation Simple derivation g m3 g m3 is determined by geometric ratios only, independent of powersupply voltages, process parameters, temperature, or any other parameters with large variability. At point A, loop gain (W L) (W L) 5 (W L) (W L) 0 eff 3 B eff 5 3 eff 3 D0 A W L W L B 3 5 B start up circuit is needed D D0 D
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-0 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit (Cont.) For a special case, g m3 B w L w 4 5 L Thus, not only is g m3 stablized, but all other transistor transconductances are also stablized since the ratios of transistor currents are mainly dependent on geometry. 3 For all n-channel transistors g mi (W L) (W L) D3 m3 For all p-channel transistors g mi n p i 3 Di (W L) (W L) i 3 g Di D3 g m3
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 Constant Transconductance Bias Circuit (Cont.) Second-order effect Body effect The equations will be slightly modified Output impedance effect Can be reduced using cascoded p-channel current mirror Temperature effect (i) μ is proportional to T -3/. This corresponds to a 7% μ reduction from 7 (300 k) to 00 (373 k) (ii) Since g m = / B and g m = μc ox (W/L) eff eff will be increased by 7% if temperature effect of B is ignored. (positive TC of B, if it is on-chip, can somewhat offset this increase) (iii) As long as eff has not been designed to be too large (or DD is large enough), this limitation is tolerable in most applications.
Widlar current sources Bipolar BE BE0 C04 EF T ln C04 C0 Trial and error todetermine 9μA C0 MOSFET O assume D0 D0 O 0 D K D0 K 4 ' O nput Stage Bias 4 4 K ' K 4 ' EF K 4 EF K EF ' K 4 ' 4 C0 4 EF Q - EE Q0 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4- 郭泰豪, Analog C Design, 08 K ' D0 0 K EF D0 4 ' EF M - EE C0 4 D0 M0 4
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-3 郭泰豪, Analog C Design, 08 Wide-Swing Constant Transconductance Bias Circuit Wide-swing current mirrors + constant g m bias circuit Q 8 Q 9 Q 0 0.6 0 0.6 Q 4 Q 7 Q 0 Q 6 0.6 0. 6 Q 0 5.6 0.6 0.6 Q 4 Q 3 Q 5 0 bias-p casc-p 0 0 Q 6 Q 8 Small W/L Q B 40 5kΩ 0 Q 3.5.6 Q 5 0 Q 0 casc-n Q 7 bias-n Bias loop Cascode bias Start-up circuitry
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-4 郭泰豪, Analog C Design, 08 Wide-Swing Constant Transconductance Bias Circuit (Cont.) Wide-swing : Minimize DS of bias transistors to eff Constant g m : g m = / B Minimization of finite output impedance effect : Use cascode bias Start-up Approximate current characteristics of the bias loop DS(Q8 ) DS(Q ) 7 DS(Q8 ) B A At point A, loop gain (W / L) (W / L) DS (Q 7 ) (W / L) (W / L) 7 8 3 4
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-5 郭泰豪, Analog C Design, 08 Wide-Swing Constant Transconductance Bias Circuit (Cont.) Start-up (Cont.) Positive feedback bias loop: Two stable points, A and B. At point A, loop gain > must be satisfied. Operational principle of start-up circuit All currents in the bias loop are zero, Q 7 will be off Q 8 is always on, the gates of Q 5 and Q 6 will be pulled high Q 5 and Q 6 will inject currents into the bias loop, which will start up the circuit. Once the loop starts up, Q 7 will be on, pulling the gates of Q 5 and Q 6 low, and thereby turning them off so they no longer affect the bias loop. This circuit is only one example of a start-up loop, and there are many other variations. For example, sometimes Q 8, is replaced by an actual resistor
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-6 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors General structure For wide-swing, bias eff out g m r ds r ds (+A) This technique for outputimpedance enhancement is not useful when bipolar Transistors (Q, Q, and Q 3 ) are used. in bias out out A out Q Q 3 Q out might be limited by db. This parasitic conductance, db, is a result of collisions between highly energized electrons resulting in electron-hole pairs to be generated with the holes escaping to the substrate. The generation of these electron-hole pairs is commonly called impact ionization.
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-7 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) A simple implementation example : regulated cascode mirror out gmrdsrds[ gm3(rds3 ro )] rds3 where rds3 ro bias t is not useful when bipolar in ro transistors are used. ds = eff3 + th (not a wide-swing source) Q 3 Q 4 Q Q out
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-8 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) Sackinger implementation in b b out Q 4 r o Q Q 6 Q 3 Q 5 Q Use regulated cascode to increase output impedance r ds3 out gmrdsrds[ gm3(rds3 ro )] where rds3 ro Q, Q, Q 3, B, out match Q 4, Q 5, Q 6, B, in, respectively. DS = DS5 = eff3 + tn rather than the minimum required, which could be equal to eff. This limitation is especially harmful for modern technologies operating with power voltages of 3.3 or lower.
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-9 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) Wide-swing + enhance output-impedance current mirrors in 7 bias 4 bias 4 bias out = in Q 5 Q 7 bias bias 70 70 0 0 Q Q 8 Q 4 Q 3 0 0 Q 80 Q 6 Level shift in front of the common source amplifier in the regulated cascode current source
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-0 郭泰豪, Analog C Design, 08 Enhanced-Output-mpedance Current Mirrors (Cont.) All transistors are biased with nearly the same current density, except for Q 3 and Q 7. As a result, all transistors have the same effective gate-source voltage, eff, except for Q 3 and Q 7, which have gate-source voltage of eff because they are biased at four times the current density. G3 = eff + tn DS = S4 = G3 - GS4 = ( eff + tn ) - ( eff + tn ) = eff out > DS + eff = eff Current Mirror Symbol Symbol A circuit example DD DD K : K
ncrease Output esistance of Current Mirrors Using Emitter/Source-Degenerated Structures Large o of current source/sink => more like ideal current source/sink For MOSFET o λ o ' W K ( )( L GS T ) ( λ DS ) For BJT AF o C S C (e BE / )( CE / AF ) Negative feedback to increase o Emitter-Degenerated Source-Degenerated App4-4- Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
ncrease Output esistance of Current Mirrors Using Emitter/Source-Degenerated Structures (Cont.) Emitter-Degenerated out in + - v be + E r π g m v be r o Δ C + Δv - o E - o (r r o [ r r [ (g o // ) [ g o ro[ (gm go)(r r [ g (r // )] o (r // ) g m g m o )(r m (r m // )] (r // )]r // )] // )] o App4- Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
ncrease Output esistance of Current Mirrors Using Emitter/Source-Degenerated Structures (Cont.) Source-Degenerated in out o + D Δ + - g m v gs S G g mb v bs r ds Δ - Similarly, r g g g r g o ds m mb ds ds m App4-3 4-3 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
ncrease o Using Wilson Current Mirror BJT r out out r in o3 β ( F3 β F β F ) out in Q 3 + out out in + Q 4 Q 3 out Q Q Q Q MOSFET out + r out r g ds3 m3 g r m3 ds (r r ds3 ds //r in ) M 4 in M 3 out M M App4-4 4-4 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
ncrease o Using Widlar Current Mirror (Cont.) Large area ratio caused by large current ratio is reduced BE ln( t in C BE ) C C in out Q + Q out terative method to obtain the value of C r out =r o (+g m ) (For CMOS implementation, Q and Q are NMOS) App4-5 4-5 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
BiCMOS Cascode Current Mirrors BiCMOS Q M o =r o (same as bipolar cascode) M o =g m r o r o =0M Q o > BE + CE(sat) (BJT) o > gs + DS(sat) (MOSFET) o > gs + CE(sat) (BiCMOS) o(bicmos) o(bjt) > o(cmos) App4-6 4-6 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
BiCMOS Double Cascode Current Mirrors BJT For =00, A =50, o =00A, r o =50M o = r o3 No improvement from cascode Q 3 Q o > BE + CE(sat) = min Q MOSFET For(W/L) =5, n C ox =40A/, =0. -, g m r o =M o =(g m3 r o3 )(g m r o )r o With same parameter as before o =40M o > GS + DS(sat) = min M 3 M M App4-7 4-7 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
BiCMOS Double Cascode Current Mirrors (Cont.) BiCMOS o =(g m3 r o3 )r o =000M Pratical limit : stray conductance o > BE + DS(sat) = min Q M 3 Q The highest o can be realized by using BiCMOS or CMOS. However, o(bicmos) > o(cmos) & min(bicmos) < min(cmos). (n general, gs > BE ) BiCMOS provides larger voltage swing. App4-8 4-8 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
Stability of Constant gm Bias (W/L) P ref bat M M :k bias_l K*(W/L) P ref SG g ref m SG μ p C μ OX p ref W L C OX P W L P ref K or 0 (W/L) N M 4 M 3 (W/L) N g m g m K DC loop gain, A 0 bat :k M M o M 4 M 3 A 0 gm gm 4 4 gm gm gm gm K K gm gm K K gm gm 3 3 positive feedback i stable at DC App4-9 4-9 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08
Stability of Constant gm Bias (Cont.) AC voltage loop gain z M DD : k M o C p o i gm gm 4 Loop gain gm gm o i 3 sc sc / g sc / g ( sc g ) m3 p p 3 P m P p Large C p Small C p m n C b M 4 M 3 C A 0 i With large C p positive feedback loop and loop gain > Unstable Pole-zero pair induced by C p and Solution: Add an on-chip capacitor at node n b, such that ω P ω Z Furthermore, C PS App4-0 4-30 z p p p 3 f p ' z ' ω Z is always less than ω P : P Z gm k ω P ω P and ω P ω P3 loop gain > the bias circuit unstable P Z g C m3 C p C g m3 C p nc C p oxn oxp Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08 (W (W L) L) M3 M C p Stability compensation criteria
Example: Stability Compensation of Constant gm Bias Constant gm bias circuit T-like 0.8μm process Parameter g m 53.5μS 0kΩ g m 96.3μS C p 3pF g m3,4 88μS C 46fF bias 7.μA C 35fF DD : k M M C p n C b M 4 M 3 C : Stability of bias circuit P g C m 7.76MHz, ω P < ω P and ω P < ω P3 unstable Stability compensation P P g C m3 304.5MHz, P3 g C m 63.MHz Add an on-chip capacitor at node n b such that ω P < ω Z C g C. 76C 5 8pF m3 p p. App4-4-3 Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 郭泰豪, Analog C Design, 08