Design & Implementation of an Adaptive Delta Sigma Modulator Shahrukh Athar MS CmpE 7 27-6-8 Project Supervisor: Dr Shahid Masud
Presentation Outline Introduction Adaptive Modulator Design Simulation Implementation Performance Evaluation Conclusion
Introduction Delta Sigma modulators are used in the design of: Analog to Digital converters (ADC) Digital to Analog converters (DAC) Frequency Synthesizers Digital Radios Oscillators They use the techniques of: Oversampling Noise Shaping
Delta Sigma Modulation Operates on the difference of the input and its predicted value Integrator or loop filter is in the feed forward path Integrator output is quantized Output sequence contains an unchanged replica of input signal along with quantization noise Demodulation requires only an appropriate low pass filter
Advantages of Oversampling and Noise Shaping Oversampling spreads the quantization noise and reduces the noise floor Noise Shaping removes quantization noise from the band of interest by pushing it out modulation incorporates oversampling and noise shaping
Higher Order Modulators High order modulators use loop filter of higher order Advantages Perform better noise shaping and remove more quantization noise from the band of interest When in stable operation they have a better SQNR and resolution Disadvantages Signal dependent quantizer gain which degrades noise shaping for large input magnitudes Performance is not uniform for time varying inputs Less stable More complex and consume more power
Multi-bit Quantizer based Modulators Multi-bit quantizer can be used instead of the single bit quantizer Advantages Can handle larger input swings Reduce quantization noise and hence increase SQNR and resolution Disadvantages Require multi-bit DACs in the modulator feedback loop which introduce non linear characteristics Require more area on chip and consume more power
Advantages of 1 st Order Single Bit Modulator Simple and robust Easy to implement Power efficient Signal independent quantizer gain Stable for varying inputs Single bit quantizer does not require multi-bit DAC Almost linear behavior
Terms used in Modulator Analysis Signal to Quantization Noise Ratio (SQNR) Resolution or Effective Number Of Bits (ENOB) Relationship between SQNR and ENOB is defined as: SQNR = 6.2 ENOB + 1.76 ENOB =.1661 SQNR -.2924
Adaptive Modulator It should adapt the amplitude of the output signal to the amplitude of the input signal Based on variations in input signal power/magnitude This project is based on the adaptive modulator design and adaptation algorithm reported by Zierhofer, C. M., in [13] and [14]. Input power can be estimated by Forward Estimation Backward Estimation Types of adaptation algorithms Syllabic Adaptation Instantaneous Adaptation
Adaptive Modulator Design Adaptation block generates the adaptive feedback signal The difference signal which is in an optimized range enters the internal 1 st order single bit modulator
Adaptation Algorithm The adaptive feedback signal should be a rough estimate of the input signal A continuous string of +1s or -1s appear at the output if tracking is lost Adaptation stage measures the local density of +1s and -1s Changes adaptive feedback signal if a threshold is crossed Adaptation Algorithm based on Instantaneous Adaptation Sample Values w(n) w(n-1) w(n-2) Adaptive Feedback Signal s(n) +1 +1 +1 s(n)=s(n-1)+bq -1-1 -1 s(n)=s(n-1)-bq All other combinations s(n)=s(n-1)
Advantages of Adaptive Modulation Uses a 1 st order single bit modulator which is stable and simple to implement Can handle input signals of larger swing Reduces quantization noise because Output is tracking the Input Input to the internal modulator is in an optimized range Power consumption is Comparable to 1 st order single bit modulator Much less than higher order modulators Output sequence is multi-level and performance is Comparable to multi-bit quantizer based modulators Uses only a Single Bit Quantizer
Simulation of the Adaptive Modulator Simulation tools used: MATLAB version 7.7..471 (R28b) Simulink version 7.2 (R28b) Modulator types simulated: Non-Adaptive 1 st Order Single Bit Modulator Adaptive Modulator Input to and Output from the modulators is sent to MATLAB workspace for evaluation of SQNR
Types of Input Signals Used Input signal 1 is a sum of five individual sinusoidal signals Individual signals have frequency components of 2KHz, 6KHz, 1KHz, 14KHz and 2KHz Input Signal 2 is a sum of five individual chirp signals Individual signals have frequency components from 1Hz to 2KHz, 6KHz, 1KHz, 14KHz and 2KHz 1 Sinusoidal Wave with f=2 KHz 1 Chirp Signal with f=1 Hz to 2 KHz -1 1 2 3 4 5 6 7 8 9 1 Sinusoidal Wave with f=6 KHz 1-1 1 2 3 4 5 6 7 8 9 1 Sinusoidal Wave with f=1 KHz 1-1 1 2 3 4 5 6 7 8 9 1 Sinusoidal Wave with f=14 KHz 1-1 1 2 3 4 5 6 7 8 9 1 Sinusoidal Wave with f=2 KHz 1-1 1 2 3 4 5 6 7 8 9 1 Summation of all Sinusoidal Waves forming the Input Signal 1 2-2 1 2 3 4 5 6 7 8 9 1-1 5 1 15 2 25 3 35 4 45 5 Chirp Signal with f=1 Hz to 6 KHz 1-1 5 1 15 2 25 3 35 4 45 5 Chirp Signal with f=1 Hz to 1 KHz 1-1 5 1 15 2 25 3 35 4 45 5 Chirp Signal with f=1 Hz to 14 KHz 1-1 5 1 15 2 25 3 35 4 45 5 Chirp Signal with f=1 Hz to 2 KHz 1-1 5 1 15 2 25 3 35 4 45 5 Summation of all Chirp Signals forming the Input Signal 2 4 2-2 -4 5 1 15 2 25 3 35 4 45 5
Simulation Model of the 1 st Order Single Bit Modulator Loop filter is defined by using the Discrete Transfer Function block Single bit quantizer is constructed using a Comparator and a D Flip Flop D Flip Flop samples at the enhanced sampling rate of 2 f b OSR
Simulation Model of the Adaptive Modulator All components of the adaptive modulator except the adaptation stage are shown here 1 st order single bit modulator used as the internal modulator
Simulation Model of the Adaptive Modulator The adaptation stage checks for five consecutive +1s or -1s [14] and is shown here It is constructed by using simple components such as delays, relational operators, switches and adders
Simulation Flow Construct Simulink Model Define Sampling Time Period according to OSR Input to the Model Run the Model Change Input Parameters Output from the Model Export Input and Output Signals to MATLAB Workspace Perform Spectral Analysis and Calculate SQNR
Implementation of the Adaptive Modulator The implementation tools used are: Xilinx System Generator for DSP v1.1 ChipScope Pro Analyzer v1.1 These tools requires prior installation of the following: Xilinx Integrated Software Environment (ISE) v1.1 MATLAB version 7.4..287 (R27a) Simulink version 6.6 (R27a) Modulator types Emulated and Implemented: Non-Adaptive 1 st Order Single Bit Modulator Adaptive Modulator
Hardware Used Memec Design Virtex-II Pro LC Development Board Xilinx XC2VP4-FG456 FPGA 1 MHz clock Oscillator PC4 JTAG Port
Xilinx System Generator for DSP Integrates itself with Simulink Ability to connect to Simulink blocks Ability to generate Verilog HDL code from models Supports Register Transfer Level implementation Supports Xilinx IP Core implementation Supports hardware Co-Simulation Supports hardware Emulation Supports Design Bitstream Generation Enables working with ChipScope Pro Analyzer
Implementation Model of the 1 st Order Single Bit Modulator 1 st order loop filter is implemented as an accumulator Single bit quantizer is implemented using a relational operator and multiplexer Simulink system period set according to the OSR Gateway In coverts the input from Simulink double to fixed point format Gateway Out converts output to Simulink double and gives it back
Implementation Model of the Adaptive Modulator All components of the adaptive modulator except the adaptation stage are shown here 1 st order single bit modulator used as the internal modulator Simulink system period set according to the OSR
Implementation Model of the Adaptive Modulator The adaptation stage checks for three consecutive +1s or -1s [13] and is shown here It is constructed by using simple components such as delays, relational operators, multiplexers and adders
Time Domain Emulation Results Non Adaptive Modulator Input Signal to the first order single bit Delta Sigma Modulator 1-1 1 2 3 4 5 6 7 8 9 1 Output Signal from the first order single bit Delta Sigma Modulator 1-1 1 2 3 4 5 6 7 8 9 1
Time Domain Emulation Results Adaptive Modulator 2 Input Signal x(n) 2 First Order Delta Sigma Sequence w(n) -2 1 2 3 4 5 6 7 8 9 1 2 Adaptive Feedback Signal S(n) -2 1 2 3 4 5 6 7 8 9 1 2 v(n)=b*w(n) -2 1 2 3 4 5 6 7 8 9 1 2 Difference Signal d(n) -2 1 2 3 4 5 6 7 8 9 1 2 Final Adaptive Delta Sigma Sequence -2 1 2 3 4 5 6 7 8 9 1-2 1 2 3 4 5 6 7 8 9 1
Time Domain Implementation Results Adaptive Modulator
Emulation Flow Construct Xilinx Model Define Simulink System Period according to OSR Simulink Input to the Model Run the Xilinx Model Change Simulink Input Parameters Output from the Model obtained in Simulink Export Input and Output Signals to MATLAB Workspace Perform Spectral Analysis and Calculate SQNR
Implementation Flow Construct the Xilinx System Generator for DSP Model Define the System Generator Parameters Generate Bitstream File Detect FPGA in ChipScope Pro Analyzer Download the Bitstream file to the FPGA Set Trigger condition & Run the Project Actual FPGA Output visible on ChipScope Pro Analyzer Export actual Input and Output Signals from ChipScope Pro Analyzer to MATLAB Workspace Perform Spectral Analysis & calculate SQNR
Performance Evaluation Spectral Analysis for Input Signals of Low Power Moderate Power High Power Spectral Analysis on data received from the FPGA Input Power versus Output SQNR Input Power versus Resolution
Amplitude Amplitude Amplitude Amplitude Spectral Analysis Spectrum of Input Signals Input Signal 1 Input Signal 2 3 Spectrum of Input Signal 1 2 Spectrum of Input Signal 2 25 2 15 15 1 1 5 5 25.9.95 1 1.5 1.1 1.15 Frequency Zoomed in Spectrum of Input Signal 1 x 1 5 2.96.98 1 1.2 1.4 1.6 1.8 Frequency Zoomed in Spectrum of Input Signal 2 x 1 5 2 15 15 1 1 5 5 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 1.34 Frequency x 1 5 1.19 1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 Frequency x 1 5
Amplitude Amplitude Amplitude Amplitude Amplitude Amplitude Spectral Analysis Low Power Input Signals Non-Adaptive Modulator Adaptive Modulator 5 Spectrum of Input Signal 5 Spectrum of Input Signal 1 2 3 4 5 6 7 8 9 1 x 1 4 Spectrum of the Delta Sigma Output Signal 5 1 2 3 4 5 6 7 8 9 1 x 1 4 Spectrum of the Delta Sigma Output Signal 5 5 4 4.5 5 5.5 6 6.5 Zoomed in Spectrum of the Delta Sigma Output Signal x 1 4 5 4 4.5 5 5.5 6 6.5 Zoomed in Spectrum of the Delta Sigma Output Signal x 1 4 4.95 5 5.5 5.1 5.15 5.2 5.25 5.3 Frequency x 1 4 4.95 5 5.5 5.1 5.15 5.2 5.25 5.3 Frequency x 1 4
Amplitude Amplitude Amplitude Amplitude Spectral Analysis Moderate Power Input Signals Non-Adaptive Modulator Adaptive Modulator 15 Spectrum of the Delta Sigma Output Signal 15 Spectrum of the Delta Sigma Output Signal 1 1 5 5 15 3 4 5 Frequency 6 7 8 x 1 4 Zoomed in Spectrum of the Delta Sigma Output Signal 15 3 4 5 Frequency 6 7 8 x 1 4 Zoomed in Spectrum of the Delta Sigma Output Signal 1 1 5 5 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 5.6 Frequency x 1 4 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 5.6 Frequency x 1 4
Amplitude Amplitude Amplitude Amplitude Spectral Analysis High Power Input Signals Non-Adaptive Modulator Adaptive Modulator 2 x 14 Spectrum of the Delta Sigma Output Signal 2 x 14 Spectrum of the Delta Sigma Output Signal 1.5 1.5 1 1.5.5 5.7.8.9 1 Frequency 1.1 1.2 1.3 1.4 x 1 5 Zoomed in Spectrum of the Delta Sigma Output Signal 5.7.8.9 1 Frequency 1.1 1.2 1.3 1.4 x 1 5 Zoomed in Spectrum of the Delta Sigma Output Signal 4 4 3 3 2 2 1 1.9.95 1 1.5 1.1 1.15 Frequency x 1 5.9.95 1 1.5 1.1 1.15 Frequency x 1 5
Magnitude Magnitude Magnitude Magnitude Spectral Analysis FPGA Operation Non-Adaptive Modulator Adaptive Modulator Non-Adaptive Delta Sigma Modulator Output 1 Adaptive Delta Sigma Modulator Output 1.5-1 -.5 2 4 6 8 1 12 14 16 Time -1 2 4 6 8 1 12 14 16 Time 3 2 1 2 4 6 8 1 12 14 16 Frequency Spectrum 3 25 2 15 1 5 2 4 6 8 1 12 14 16 Frequency Spectrum
SQNR (db) Input Power VS SQNR (Input 1 Simulation) 8 7 6 5 4 3 2 1-6 -4-2 2 4 6 8 1-1 -2-3 Input (db) Non Adaptive Modulator Adaptive Modulator
SQNR (db) Input Power VS SQNR (Input 2 Emulation) 4 3 2 1-6 -4-2 2 4 6-1 -2-3 Input (db) Non Adaptive Modulator Adaptive Modulator
Effective Number of Bits (ENOB) Input Power VS ENOB (Input 1 Simulation) 12 1 8 6 4 2-6 -4-2 2 4 6 8 1-2 -4-6 Input (db) Non Adaptive Modulator Adaptive Modulator
Effective Number of Bits (ENOB) Input Power VS ENOB (Input 2 Emulation) 6 5 4 3 2 1-6 -4-2 2 4 6-1 -2-3 -4-5 Input Power (db) Non Adaptive Modulator Adaptive Modulator
Conclusion An adaptive modulator was successfully simulated and implemented Its notable characteristics are: Stability and simplicity of a 1 st order single bit modulator Performance comparable to 2 nd order modulators Multi-bit Quantizer based modulators Ability to handle larger input swings Ability to handle signals with low and high power better than the corresponding non-adaptive modulator Better SQNR and Resolution when compared to the corresponding non-adaptive modulator
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