WebHenry Web Based RLC interconnect tool http://eda.ece.wisc.edu/webhenry Project Leader: Prof Lei He Students : Min Xu, Karan Mehra EDA Lab (http://eda.ece.wisc.edu] ECE Dept., University of Wisconsin, Madison, WI 53706 Adapted from Min Xu s GLS 01 presentation
REFERENCES [1] L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", IEEE Custom Integrated Circuits Conference, May 1999. [2] N. Chang, S. Lin, L. He, O. S. Nakagawa, and W. Xie, "Clocktree RLC extraction with Efficient Inductance Modeling", IEEE/ACM Design Automation and Test in Europe, March 2000. [3] Min Xu and Lei He, "An efficient model for frequencybased on-chip inductance," Design Automation Conference, June. 2
Inductance for GHz Designs Interconnect impedance is more than resistance Z = R +jωl ω is decided not by the clock frequency, but by clock edge ω 1/tr On-chip inductance must be considered when ωl is comparable to R Inductive coupling is a long range effect 3
Resistance and Inductance L S W W L = 2000u, W = 0.8u, T = 2.0u, S = 0.8u 200 3.20E-09 Impedance 180 160 140 120 100 80 60 R wl Inductance(H) 3.10E-09 3.00E-09 2.90E-09 2.80E-09 2.70E-09 Self mutual 40 2.60E-09 20 2.50E-09 0 1.00E+08 1.00E+09 1.00E+10 1.00E+11 1.00E+08 1.00E+10 1.00E+12 1.00E+14 frequency (100M-100G) frequency (100M-100T)Hz Figure 1: R and wl L for a single long wire Figure 2: Ls and Lx for two parallel wires 4
Related Work Accurate but slow approach Numerical extraction (FastHenry: Kamon et. al.94 MTT) Too slow to be applied on whole chip level simulation and design iteration Fast but less accurate approach Table method for bus structure (He et. al. 99 CICC) Analytical methods for parallel wires (Gala et. al. 00 and Qi et. al. 00 ) Accurate enough for layout design and verification 5
Our Contributions Developed a table & formula driven extraction tool For arbitrary wires Accuracy: ±5% for most cases http://eda.ece.wisc.edu/webhenry/ Proposed the so called normalized circuit model to replace full RLC circuit Experimentally verified their equivalence Less complexity and shorter runtime: 11x speedup in simulation 6
Definition of Loop Inductance I i I j V i V j The loop inductance is L ij = µ 4π 1 a a i j 1 I I i j loop a i i loop a ij j j 1 di r i di j da i da j 7
Loop Inductance for N Traces Tw L Ts L Tw Tw Tw Ts Ts Ts R Tw R t L t 1 t 2 t 3 t R 1.73 1.15 0.53 1.15 1.94 1.24 0.53 1.24 1.92 Assume edge traces are grounded leads to 3x3 loop inductance matrix Inductance has a long range effect e.g., non-negligible coupling between t 1 and t 3 with t 2 between them 8
Table in Brute-Force Way is Expensive Tw L t L Ts L Tw Tw Tw Ts Ts t 1 t 2 t 3 Ts R Tw R Self inductance has nine dimensions: (n, length, location,tw L,Ts L,Tw,Ts,Tw R,Ts R ) Mutual inductance has ten dimensions: (n, length, location1, location2,tw L,Ts L,Tw,Ts,Tw R,Ts R ) Length is needed because inductance is not linearly scalable t R 1.73 1.15 0.53 1.15 1.94 1.24 0.53 1.24 1.92 9
Definition of Partial Inductance c i c j V i l i lj V j b i b j Partial inductance is the portion of loop inductance for a segment when its current returns via the infinity called partial element equivalent circuit (PEEC) model If current is uniform, the partial inductance is L ij = µ 4π 1 a a i j c i j b a i i c b a j j dl i r dl ij j da i da j 10
Partial Inductance for N Traces Tw L Ts L Tw Tw Tw Ts Ts Ts R Tw R tl t 1 t 2 t 3 t R 6.17 5.43 5.12 4.89 4.66 5.43 6.79 6.10 5.48 5.04 5.12 6.10 6.79 6.10 5.33 4.89 5.48 6.10 6.79 5.77 4.66 5.04 5.33 5.77 6.50 Treat edge traces same as inner traces lead to 5x5 partial inductance table Partial inductance model is more accurate compared to loop inductance model 11
Two Foundations By PEEC Definition, He et. al. (CICC 99) pointed out two foundations: Self inductance of a wire is solely depended on the wire itself Mutual inductance of two wires is solely depended on these two wires themselves 12
Table-based approach (He et. el. 99 CICC) Inductance table for parallel wires Self inductance table Length -- L Width -- W Thickness -- T Frequency -- F Mutual inductance table L, W, T, F Space -- S 13
Displaced parallel wires? Based on foundation for mutual inductance: Solve ten dimensional problem L1, L2, W1, W2, T1, T2, Sv, Sh, D, F Too big, too slow A formula is proposed to use only five dimensional tables 14
Formula for Lateral Dimension L ab = a b Mutual inductance + - - L m1 L m2 L m3 L m4 15
Formula for Cross-section Linear approximation T 2 w 2 s + s w 1 s 2 T 1 16
Accuracy WebHenry versus FastHenry 400 random displaced parallel wires cases 17
Error Distribution 5% most cases Bigger error only found in smaller inductance values 18
Inductance Circuit Modeling Full and normalized circuit model for nondisplaced parallel wires 19
Full RLC Circuit Model Linear RC number Quadratic L number, O(n 2 ) 20
Normalized RLC Circuit Model Again, linear RC number Linear L number too! 21
Full Versus Normalized Two waveforms are almost identical Running time: Full 99.0 seconds Normalized 9.1 seconds 22
Applications Simultaneous shield insertion and net ordering for signal integrity [He-Lepak, ISPD 00] [Lepak-et al, DAC 01] Interconnect analysis using decoupling model [Yin-He, ASP-DAC 01] Simultaneous signal and power routing [Ma-He, SLIP 01] 23
Conclusion A table-formula driven extraction method is proposed Very efficient Reasonably accurate Frequency dependent Two circuit models are studied Verified the normalized model is accurate and efficient 24
25
On-chip Inductance Wire impedance: Z = R + jϖl Copper interconnects makes R ϖ is proportional to signal rising time 1 GHz clock ϖ = 2π*10GHz Inductive coupling is a long range effect Partial inductance model is preferred. Let the circuit simulator to determine the signal return path 26
The PEEC Model Eliminate the current return path problem L (loop) I 1 I 2 L 1 I 3 K 13 K 12 K 23 L 2 I 1 I 2 I 4 Assume current return from infinite L 3 27