Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 Powe Reduction and Speed Augmentation in LFSR fo Impoved Sequence Geneation Using Method Vikas Sahu, M. Padeep Kuma M.Tech.(Digital Electonics) RCET, Bhilai, India, Asst. Pof. ET&T Dept., RCET, Bhilai, India Abstact-In many electonics cicuit Linea Feedback Shift Registe (LFSR) used fo geneating sequences. So fo high pefomance applications LFSR should have to geneate efficient sequences. Thee ae so many methods of geneating vey efficient sequences. The demand and populaity of potable LFSR is diving designes to stive fo small silicon aea, highe speeds, low powe dissipation and eliability. Compaed to static LFSR, dynamic LFSR offes good pefomance. Wide fan-in logic such as domino LFSR is used in high-pefomance applications. Dynamic domino LFSRs ae widely used in moden digital VLSI cicuits. These dynamic LFSRs ae often favoed in high pefomance designs because of the speed advantage offeed ove static LFSR cicuits. This pape compaes diffeent types of LFSR on the basis of pefomance paamete such as powe consumption, popagation delay and leakage cuent at 65 nm, 45 nm, 32 nm and 25nm technologies fo high pefomance LFSR design. The techniques ae compaed by pefoming detailed tansisto simulations on benchmak cicuits using Micowind 3 and DSCH 3 CMOS layout CAD tools. Key wods- LFSR, Leakage cuent, Powe dissipation, Popagation Delay and VLSI. I. Intoduction An LFSR is a shift egiste that, when clocked, advances the signal though the egiste fom one bit to the next most-significant bit. Some of the outputs ae combined in exclusive-or configuation to fom a feedback mechanism. A linea feedback shift egiste can be fomed by pefoming exclusive-or on the outputs of two o moe of the flip-flops togethe and feeding those outputs back into the input of one of the flip-flops. The aim of this pape is to compaes static LFSR, domino (dynamic) LFSR and diffeent types of LFSR which ae designed by diffeent components (Tansmission gates and invete, tansistos) on the basis of pefomance paamete such as powe consumption, delay, powe delay poduct, no of tansistos use and leakage cuent at 65 nm, 45 nm, 32 nm and 25nm technologies. II. Powe Dissipation The powe consumed by CMOS cicuits can be classified into two categoies: A. Dynamic Powe Dissipation Fo a faction of an instant duing the opeation of a cicuit, both the PMOS and NMOS devices ae on simultaneously. The duation of the inteval depends on the input and output tansition (ise and fall) times. Duing this time, a path exists between VDD and GND and a shot-cicuit cuent flows. Howeve, this is not the dominant facto in dynamic powe dissipation. The majo component of dynamic powe dissipation aises fom tansient switching behaviou of the nodes. Signals in CMOS devices tansition back and foth between the two logic levels, esulting in the chaging and dischaging of paasitic capacitances in the cicuit. Dynamic powe dissipation is popotional to the squae of the supply voltage. In deep sub-micon pocesses, supply voltages and theshold voltages fo MOS tansistos ae geatly educed. This, to an extent, educes the dynamic powe dissipation. [15] B. Powe Dissipation This is the powe dissipation due to leakage cuents which flow though a tansisto when no tansactions occu and the tansisto is in a steady state. Leakage powe depends on gate length and oxide thickness. It vaies exponentially theshold voltage and othe paametes. Reduction of supply voltages and theshold voltages fo MOS tansistos, which helps to educe dynamic powe dissipation, becomes disadvantageous in this case. The sub theshold leakage cuent inceases exponentially, theeby inceasing static powe dissipation. [15] Fomula fo Powe Dissipation: P d = (I avg ) (V dd ) [16] Whee, I avg = aveage cuent, V dd = applied voltage. ISSN: 2231-2803 http://www.ijcttjounal.og Page 560
Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 Whee, Fomula fo Leakage Cuent: I leakage = I 0 exp( v gs -v th )/n v t [17] Hee, I 0 = µ 0 C ox [W/L]V t 2 e 1.8 Fomula fo Popagation delay: T pd α (V dd /(V dd -V th ) 2 ) [18] C ox = Gate oxide capacitance, (W/L) = Width to length atio of device, µ 0 = Zeo bias mobility, V gs = Gate to souce voltage, V t = Themal voltage and n=2 (Sub-theshold swing coefficient) T pd = Popagation delay V dd = Supply Voltage V th = Theshold Voltage III. PROBLEM IDENTIFICATION the leaking MOS Fo diving the MOSFET (Metal Oxide Semiconducto Field effect tansisto) key paamete is the scaling of the tansisto gate length, which has a significant pefomance impact at the 32nm node & beyond. Because of the lage gate tunnelling cuents, the gate oxide cannot be futhe scaled down and beyond the 45nm node the channel length scaling out gate dielectic scaling actually degades tansisto dive cuent and pefomance. Fo futhe eduction in scaling technology beyond the 45nm node the high-k dielectic mateial is intoduced as gate dielectic laye. As the gate oxide thickness of a tansisto educes, pefomance of the tansisto become poo. This will give the negative impact on all ove pefomance of the CMOS logic cicuit. Fo achieving this pupose semiconducto enginees have continuously deceases the thickness of the gate dielectic laye, highe leakage cuent will be esulted in the educed dielectic thickness. stacked on top of each othe [Refe Fig.1], and then they dissipate less leakage powe than a single tansisto that is tuned OFF [Refe Fig.1]. This is because each tansisto in the stack induces a slight evese bias between the gate and souce of the tansisto ight below it, and this inceases the theshold voltage of the bottom tansisto making it moe esistant to leakage. Theefoe in Fig.10a tansisto T 2 leaks less cuent than tansisto T1 and T 3 leaks less than T 2. Hence the total leakage cuent though the tansistos T 1, T 2 and T 3 is deceased as it flows fom V dd to Gnd. So I leak1 is less than I leak2. If natual stacking of tansistos does not exist in a cicuit, then to utilize the stacking effect a single tansisto of width W is eplaced by two tansistos each of width W/2. The poposed D flip-flop cicuit using stacking effect is shown in Fig.2. The leakage eduction achievable in a two-stack compising of devices widths Wu and W l compaed to a single device of width w is given by equation 5. [22] X = I w = I w w 10 λ V (1 ) s.(1) Whee =.(2) λ is the dain-induced baie loweing (DIBL) facto and s is the sub-theshold swing coefficient. When w u = w l = w/2 then the leakage eduction facto o stack effect facto X is ewitten as X = 10 ( ) X = 2 10 ( ).(3)...(4) X = 2 10...(5) Whee u is the univesal two-stack exponent which depends only on the pocess paamete, λ and s, and the design paamete V dd. Thus the leakage cuent though a single OFF device is geate than leakage though a stack of two OFF devices. Leakage powe has become a seious concen in nanomete CMOS technologies. In the past, the dynamic powe has dominated the total powe dissipation of CMOS devices. Howeve, the continuous tend of technology scaling, leakage powe is becoming a main contibuto to powe consumption. IV. PROPOSED METHODOLOGY A. Using Stack The leakage cuent flowing though a stack of seies connected tansistos educes when moe than one tansisto of the stack is tuned OFF. This effect is known as the Effect [21].When two o moe tansistos that ae switched OFF ae Fig.1. stacking effect [21] ISSN: 2231-2803 http://www.ijcttjounal.og Page 561
Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 Fig.2. D flip-flop tansisto stacking [21] Hee fou types of cicuits ae used which ae given below. 1) Cicuit The pinciple of static CMOS logic is shown in Fig.3 the output is connected to gound though an n-block and to V DD though a dual p-block. Without changes of the inputs this gate consumes only the leakage cuents of some tansistos. When it is switching it daws an additional cuent which is needed to chage and dischage the intenal capacitances and the load. Although the gate's logic function is ideally independent of the tansisto channel widths, they detemine the dynamic behaviou essentially. Wide tansistos will switch a capacitive load faste, but they will also cause a lage input capacitance of the gate. Unless othewise noted, minimum-width and, of couse, minimumchannel-length tansistos ae assumed. Fo given capacitances the tansistos' on-state cuent I ON will limit the switching speed of the gate and, consequently, the maximum clock fequency of a synchonous cicuit. Two othe impotant paametes detemining the speed ae the so-called fan-in F in which is the numbe of inputs of a gate, and the fan-out V out which is the numbe of unity loads (i.e., inputs) connected to a gate's output [19]. Advantages of Cicuits High noise magins. Low output impedance, high input impedance. No steady state path between V DD and GND (no static powe consumption). Delay a function of load capacitance and tansisto esistance compaable ise and fall times (unde the appopiate tansisto sizing conditions). 2) Dynamic Cicuit Dynamic logic cicuits offe seveal advantages in ealizing highdensity, high pefomance digital system whee eduction of cicuit delay and silicon aea is impotant. Opeation of all dynamic logic gates depend on tempoay stoage of chage in paasitic node capacitances, instead of elying on steady-state cicuit behavio. Dynamic logic cicuits equie peiodic clock signals in ode to contol chage efeshing. Dynamic logic techniques save aea by educing the numbe of tansistos pe gate, and save powe by educing the numbe of gates and the static cuent in stuctues such as flip-flops & shift egistes. Dynamic CMOS cicuits save chip aea while enhancing speed ove conventional CMOS cicuits, but pecautions must be taken to ensue pope opeation. Use of common clock signals the system enables synchonize the opeation of vaious cicuit blocks. Capability of tempoaily stoing a state at a capacitive node allows implementing simple sequential cicuits memoy functions. Disadvantage of dynamic stoage is the use of small-sized, leaky capacitos fo stoing logic values. They must be clocked at a minimum opeating fequency in ode to maintain thei chage. In Dynamic CMOS logic, I DD Path is tuned off when clockdisabled and/o the output is evaluated when clock enabled. Cicuit opeation is based on fist pe-chaging the output node capacitance and evaluating the output level accoding to the applied inputs as shown in figue 4. Both opeations ae scheduled by a single clock signal which dives one nmos and one pmos tansisto in each dynamic stage. Figue 4. Dynamic Cicuit [19] 3) Cicuit The pass tansisto, MP is diven by peiodic clock signal and acts as access switch to eithe to chage up o down the paasitic capacitance C x, depending on V in. Two opeations ae possible when CK = 1. 1 tansfe and logic 0 tansfe. The output of depletion-load nmos invete depends on voltage V x. MP povides only cuent path to the intemediate capacitive node (soft node) X. When CK = 0, the MP ceases to conduct and chage stoed in the paasitic capacito C x continues to detemine output level of the invete. Figue 3. Cicuit [19] i. 1 Tansfe If the soft node voltage is equal to 0 initially, i.e., V x (t = 0) = 0 V. 1 level is applied to the input teminal, which coesponds to V in = V DD. When CK changes fom 0 to 1, MP ISSN: 2231-2803 http://www.ijcttjounal.og Page 562
Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 will be in satuation. The equivalent cicuit fo logic 1 tansfe is shown in figue 5. The diection of cuent flow though will be opposite to that duing chage-up event. The pass tansisto MP opeating in the linea egion dischages the paasitic capacito C x as follows: C dv dt = k 2 (2(V V, )V V ) Integating above equation w..t. t we get, t = C k (V V, ) ln (2V V, V V ) Figue 5. Equivalent cicuit fo logic 1 tansfe Vaiation of node voltage V x w..t. last equation is plotted as function of time is shown in figue 8. The pass tansisto MP opeating in the satuation egion stats to chage up the capacito C x, since, I = C dv/dt. Thus, Then Vx(t) is C dv dt V V, = k 2 (V V V, ) V (t) = k V 2C V, t 1 + k 2C V V, t Vaiation of node voltage V x w..t. last equation is plotted as a function of time is shown in figue 6. ii. Figue 6. Vaiation of node voltage as a function of time duing logic 1 tansfe 0 Tansfe If the that soft node voltage is equal to 1 initially, i.e., V x (t = 0) = V max = (V DD V T,n ). 0 level is applied to the input teminal, which coesponds to V in = 0 V. When CK changes fom 0 to 1, MP will be in linea egion. The equivalent cicuit fo logic 0 tansfe is shown in figue 7. Figue 8. Vaiation of node voltage as a function of time duing logic 0 tansfe. Fall time fo the soft node voltage V x can be calculated fom pevious equation. C τ = 2.74 k (V V, ) Advantages of pass tansistos ae: They ae not atio devices and can be minimum geomety. They do not have a path fom plus supply to gound, do not dissipate standby powe. They ae used as function block. Vey efficient in use of tansisto. Potentially vey efficient layouts esults. tansistos can usually be minimum size devices. Usually moe intenal node capacitance than conventional CMOS gates. Popagation delays can become lage in long seies stings of pass tansistos. powe dissipation is unaffected. Dynamic powe dissipation may be deceased. The disadvantage of pass tansisto logic cicuit is that if the theshold voltages of all tansistos ae same, then the node voltage at the end of the pass tansisto chain will become one theshold voltage lowe than V DD, egadless of numbe of pass tansistos in chain. [19] Figue 7. Equivalent cicuit fo logic 0 tansfe 4) Tansmission Gate Cicuit CMOS TG consists of one nmos and one pmos tansisto connected in paallel is shown in figue 9. CMOS TG opeates as a bidiectional switch between the nodes A and B which is contolled by signal C. If C is high, both the tansistos ae tuned on and povide a low esistance cuent path between the nodes A & B. If C is low, both the tansistos ae tuned off and path between the nodes A & B will be an open cicuit, called highimpedance state. ISSN: 2231-2803 http://www.ijcttjounal.og Page 563
Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 Table. 2. Powe Dissipation 65nm 15.35 8.41 Tansmis sion Gate and Invete 23.787 17.528 Figue 9. CMOS Tansmission Gate [19] A CMOS tansmission gate can be constucted by paallel combination of NMOS and PMOS tansistos, complementay gate signals. The main advantage of the CMOS tansmission gate compaed to NMOS, tansmission gate is to allow the input signal to be tansmitted to the output out the theshold voltage attenuation. V. OUTPUT In this pape CMOS implementations of LFSRs using static logic cicuit, dynamic logic cicuit, pass tansisto logic cicuit, and tansmission gate logic cicuit ae designed. This LFSR design using pass tansisto logic has the maximum delay, minimum aveage powe and use maximum numbe of tansistos. The leakage powe and leakage cuent of all the designs ae decease when eduction techniques ae applied. The pecentage eduction of leakage powe is moe the poposed tansisto stacking technique. The design using Tansmission gate logic cicuit and Dynamic logic ae given least delay and Dynamic logic cicuit is use less numbe of tansistos then othes. The design of LFSR using pass tansistos tansisto stacking technique is give the minimum leakage powe and leakage cuent. But, if the theshold voltages of all tansistos ae same, then the node voltage at the end of the pass tansisto chain is become one theshold voltage lowe than VDD, egadless of numbe of pass tansistos in chain. So that due to this disadvantage of pass tansisto we use dynamic logic cicuit tansisto stacking fo designing high pefomance LFSR. Table. 1. Powe Dissipation 65nm 0.302 0.324 33.87 45 nm 32 nm 33.311 20.681 25 nm 6.047 33.590 21.093 5.164 14.155 5.317 3.399 3.737 2.330 1.73 0.865 45 nm 4.452 2.336 11.65 9.150 32 nm 3.662 1.889 7.274 5.70 25 nm 0.695 0.41 Table. 3. Leakage Cuent 1.537 1.175 65nm 0.431mA 0.46 ma 0.048mA 0.02 ma 45 nm 0.083mA 0.084mA 0.013mA 0.008mA 32 nm 0.059mA 0.060mA 0.011mA 0.007mA 25 nm 2.419mA 2.065mA 0.709mA 0.864mA Table. 4. Leakage Cuent Tansmis sion Gate and Invete 65nm 0.022 ma 0.012mA 0.034mA 0.025mA 45 nm 0.011mA 0.006mA 0.029mA 0.023mA 32 nm 0.010mA 0.005mA 0.021mA 0.016mA 25 nm 0.278mA 0.164mA 0.615mA 0.47 ma ISSN: 2231-2803 http://www.ijcttjounal.og Page 564
Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 Table. 5. Popagation Delay in 32 nm 32 nm 16ps 42ps 16ps 20ps Table. 6. Popagation Delay in 32 nm Tansmis sion Gate and Invete 32 nm 38ps 42ps 17ps 25ps Fom the whole system design and pefomance analysis it can be easy to conclude that system designed on 32nm scale will always give vey high pefomance in compaison to othe. 1000 900 800 700 600 500 400 300 200 100 0 65 nm 45 nm 32 nm 25 nm Figue 10. Powe Dissipation (Mico Watt) in Diffeent Technology SL SL TS DL DL TS PTL PTL TS TG&IL TG&IL TS Table. 7. No. of s 45 90 44 88 Table. 8. No. of s Tansmissio n Gate and Invete 60 120 56 112 3 2.5 2 1.5 1 0.5 0 SL SL TS DL DL TS PTL PTL TS TG&IL TG&IL TS 65 nm 45 nm 32 nm 25 nm Figue 11. Leakage Cuent (ma) in Diffeent Technology VI. APPLICATION The application of LFSRs ae given below Pseudo-noise sequences Fast digital countes Whitening sequences Patten Geneatos Built-in Self-Test (BIST) Encyption Compession Checksums Pseudo-Random Bit Sequences (PRBS) VII. CONCLUSION On the basis of the whole pefomance the tansisto logic has minimum powe dissipation and leakage cuent but it cannot be cascaded each othe so that domino/dynamic logic is used fo designing high pefomance LFSR. REFERENCES [1] Kelin J. Kuhn, CMOS Scaling Past 32nm and Implications on Vaiation, IEEE jounal of Advanced Semiconducto Manufactuing Confeence (ASMC), pp 241-246, Aug 2010. [2] http://www.niconpecision.com/eeview/sping_2010/ aticle05.html. [3] S. Nataajan, A 32nm Technology Featuing 2nd- Geneation High-k + Metal-Gate s, Enhanced Channel Stain and 0.171µm2 SRAM Cell Size in a 291Mb Aay, IEEE jounal of electon Device Meeting (IEDM), pp 1-3, Feb 2009. [4] Yasuo Naa, Scaling Challenges of MOSFET fo 32nm Node and Beyond, IEEE Jounal of VLSI Scaling, Systems & Application. pp 72-73, apil 2009. [5] Xinlin Wang, Ghavam Shahidi, Phil Oldiges and Mukesh Khae, Device Scaling of High Pefomance MOSFET Metal Gate High-K at 32nm Technology Node and Beyond, IEEE Jounal of simulation of semiconducto pocesses and devices (SISPAD), pp 309-312, sep 2008. [6] Chattopadhyay, Low Powe Design Techniques fo Nanomete Design Pocesses - 65nm and Smalle, IEEE Confeence on VLSI Design, pp 5-5, feb 2007. [7] KAUSHIK ROY, SAIBAL MUKHOPADHYAY, HAMID MAHMOODI MEIMAND, Leakage Cuent Mechanisms and ISSN: 2231-2803 http://www.ijcttjounal.og Page 565
Intenational Jounal of Compute Tends and Technology (IJCTT) - volume4issue4 Apil 2013 Leakage Reduction Techniques in Deep-Submicomete CMOS Cicuits, poceedings of IEEE, pp 305-327, apil 2003. [8] Tadayoshi Enomoto, Yoshinoi Oka, and Hioaki Shikano, (2003), A Self-Contollable Voltage Level (SVL) Cicuit and its Low- Powe High-Speed CMOS Cicuit Applications, IEEE Jounal of Solid State Cicuits, Vol. 38, No.7, pp.1220-1226. [9] Chandakasan, A.P. Bodesen, Minimizing powe consumption in digital CMOS cicuits, unde the Poceedings of the IEEE. pp 498-523, aug 2002. [10] Richad X. Gu, Mohamed I. Elmasy, Powe Dissipation Analysis and Optimization of Deep Submicon CMOS Digital Cicuits, IEEE jounal of Solid-State Cicuits, pp 707-713, aug 2002. [11] P. Sivastava, A. Pua, and L. Welch,.Issues in the Design of Cicuits, Poceedings of the IEEE Geat Lakes Symposium on VLSI, pp. 108-112, Febuay 1998. [12] G. Balamuugan and N. R. Shanbhag,.Enegy- efficient Dynamic Cicuit Design in the Pesence of Cosstalk Noise,. Poceedings of the IEEE Intenational Symposium on Low Powe Electonics and Design, pp. 24-29, August 1999. [13] V. Stojanovic and V.G. Oklobdzija, (1999), Compaitive Analysis of Maste Slave Latches and Flip-Flops fo High-pefomance and Low-Powe systems, IEEE Jounal of Solid State Cicuits, Vol. 34,No.4, pp.536-548. [14] Linfeng Li and Jianping Hu, (2009), A Tansmission Gate Flip- Flop Based on Dual Theshold CMOS Techniques, Poceedings of IEEE Intenational Symposium on Cicuits and Systems (ISCAS2009), pp. 539-542. [15] SALENDRA.GOVINDARAJULU*1, DR. T.JAYACHANDRA PRASAD2, Design of High Pefomance Dynamic CMOS Cicuits in Deep Submicon Technology, Salenda Govindaajulu et. al. / Intenational Jounal of Engineeing Science and Technology Vol. 2(7), 2010, 2903-2917. [16] Pooja Vaishnav and M. Vishal Moyal Pefomance Analysis Of 8-Bit ALU Fo Powe In 32 Nm Scale Intenational Jounal of Engineeing Reseach & Technology (IJERT) Vol. 1 Issue 8, Octobe 2012 ISSN: 2278-0181. [17] R. Iis Baha, Low Powe VLSI System Design Lectue 6: State Machine Optimization & MTCMOS, bown. [18] M. Janaki Rani1 and S. Malakann2, LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS, Intenational Jounal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, Febuay 2012. [19] VLSI Design by A.Shanthi Kavita. [20] Pincipal of VLSI design by Neil H.E.Weste. [21] Doshi N. A, Dhobale S. B, and Kakade S.R, 2008, LFSR Counte Implementation in CMOS VLSI, Wold Academy of Science, Engineeing and Technology 48, 2008. [22] Siva Naenda, ShekhaBoka,Vivek De, Dimiti Antoniadis, and Anantha Chandakasan,(2001) Scaling of Stack Effect and its Application fo Leakage Reduction, ISLPED 01, pp. 195-200. [23] M.C. Johnson, D.Somasekha, L.Y. Chiou, and K.Roy, (2002), Leakage Contol Efficient Use of tansisto Stacks in Single theshold CMOS, IEEE Tansactions on Vey Lage Scale Integation (VLSI) Systems, Vol. 10, No. 1, pp. 1-5. [24] Yuan Chen, Scaled CMOS Technology Reliability, by Califonia Institute of Technology, and was sponsoed by the National Aeonautics and Space Administation Electonic Pats and Packaging (NEPP) Pogam, 2008. [25] Technology backgounde: High-k gate oxides, by IC Knowledge, 2002. [26] Abhishek Kuma, LEAKAGE CURRENT CONTROLLING MECHANISM USING HIGH K DIELECTRIC + METAL GATE, Intenational Jounal of Infomation Technology and Knowledge Management, pp. 191-194, Januay-June 2012. [27] http://www.review intel 45nm technology.com [28] http://en.wikipedia.og/wiki/immetionlithogaphy. Categoies: Lithogaphy (mico fabication). [29] Xin Wu, Pabhuam Gopalan, and Geg Laa, Xilinx Next Geneation 28 nm FPGA Technology Oveview, by Xilinx white pape. [30] N. When and M. Munch, Minimization Powe Consumption in Digital Cicuits and Systems: an oveview, IEEE Confeence on High Pefomance System Design: Cicuit and, pp 169-259, 1999. Vikas Sahu eceived the B.E. degee in Electonics and Telecommunication engineeing fom MPCCET,Bhilai (Pt. Ravi Shanka Shukla Univesity, Raipu, C.G.) in 2008. He is cuently pusuing M.Tech. in Digital Electonics fom RCET, Bhilai, C.G. (Chhattishgah Swami Vivekananda Technical Univesity, Bhilai, C.G.). His technical inteests include Low Powe and High Speed CMOS VLSI Design. Padeep Kuma eceived the B.E degee fom MPCCET, Bhilai (Pt. RSU, Raipu, CG) in 2006, MTech in Digital Electonics fom CSVTU, Bhilai, pesently woking as Assistant Pofesso in RCET, Bhilai. His technical inteests include data convesion, powe management, and baseband analog integated cicuits. ISSN: 2231-2803 http://www.ijcttjounal.og Page 566