TDDB Time Depending Dielectric Breakdown. NBTI Negative Bias Temperature Instability. Human Body Model / Machine Model

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For integrated circuits or discrete semiconductors select Amkor-Kr to ASECL Assembly Transfer with Cu wire bonds ID Type of change No Yes AC TC SD Headings ANY A2 A3 A4 A5 A6 B1 B2 B3 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 E2 E3 E4 E5 E7 E9 E10 E11 E12 G1-4 G5 G6 G7 G8 3 4 5 6 7 8 9alt 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Headings Headings Headings Headings Headings Headings Headings Headings Headings I below: DATA SHEET DESIGN PROCESS - WAFER PRODUCTION BARE DIE PROCESS - ASSEMBLY Change of wire bonding Change in process technology (e.g., die attach, bonding, moulding, plating, trim and form, lead frame preperation, ) PACKING/SHIPPING EQUIPMENT TEST FLOW Q-GATE Form provided by ZVEI Revision 2.1 03/2015 e. g. change from Au to Cu material Material, diameter, change in process technique e. g. change from 25µm to 23µm diameter and / or bonding diagram e. g. change from single to double bond e.g. change to green mold compound e. g. change of filler particles e. g. change from inked marking to laser marking e. g. marking of pin 1 e. g. change of appearance (additional marking) (--): If the change in process technology does not influence the integrety of the final product. (P): If the change in process technology can influence the integrety of the final product. A = impact of thermo mechanical stress caused by mismatch of mold compound, interconnecting technology and carrier is evident. Please also check changes described under EQUIPMENT (SEM-EQ-01). A or B = impact on other type of changes described under PROCESS ASSEMBLY and EQUIPMENT (SEM-EQ-01). Device does PD LI EM SM LU N/A N/A N/A N/A N/A N/A N/A ED SC LF LT DS EV PV TC AC IOL PD TS CA MS SD TR BS DS UIS DI Parameter Analysis: Strictly required only for Power devices. In general: Site audit for material change with impact on bondprocess (e.g. from Au to Cu) recommended. AEC-Q100: "For broad changes that involve multiple attributes (e.g., site, materials, processes), refer to section A1.3 of this appendix and section 2.3 of Q100, which allows for the selection of worst-case test vehicles to cover all the possible permutations." Whisker tests have to be done on monitoring basis! AEC-Q100: "For broad changes that involve multiple attributes (e.g., site, materials, processes), refer to section A1.3 of this appendix and section 2.3 of Q100, which allows for the selection of worst-case test vehicles to cover all the possible permutations." Worked on: (Name, Function) Date: 1-Apr-15 PCN number: 16157B Signature: Bobby Mays Device evaluation AEC-Q100 Revision H MATERIAL PERFORMANCE TEST RESULTS (on the basis of AEC-Q100 Revision H) includes integrated circuits (e.g. ASICs, µ-controler, memories, voltage regulators, smart power devices, logic devices, analog devices,... ) MATERIAL PERFORMANCE TEST RESULTS (on the basis of AEC-Q101 Revision D) includes e.g. small signal diodes (bipolar - and Schottky diodes), small signal transistors, MOSFETS, IGBTs, power diodes, additional to AEC-Q10x Hide Text Values: Hide Columns Values: Show Rows Assessment of impact on Supply Chain regarding following aspects Remaining - contractual agreements risks on - technical interface of processability/manufacturability of customer Supply - form, fit, function, quality performance, reliability Chain? Understanding of semiconductors Examples to explain Mark change experts with an "x" A: Application level B: Boardlevel Evaluation level C: Component level A / B / C *: will become A/B/C after decision Further applicable conditions Line evaluation (can be evaluated by data or audit/on site check) AEC-Q100 Revision H Check of specification (for raw material only) THB Temperature Humidity Bias or biased HAST Autoclave or Unbiased HAST Temperature Cycling PTC Power Temperature Cycling HTSL High Temperature Storage Life HTOL High Temperature Operating Life ELFR Early Life Failure Rate EDR NVM Endurance, Data Retention, and Operational Life WBS Wire Bond Shear WBP Wire Bond Pull Solderability Physical Dimensions SBS Solder Ball Shear Lead Integrity Electromigration TDDB Time Depending Dielectric Breakdown HCI Hot Carrier Injection NBTI Negative Bias Temperature Instability Stress Migration Electronic Discharge HBM/MM Human Body Model / Machine Model Electronic Discharge CDM Charged Device Model Latch up Electrical Distribution CHAR Characterisation EMC Electromagnetic Compatibility Short Circuit Characterization SER Soft Error Rate Lead free MECH Hermetic Package Test DROP Package Drop Lid Torque Die Shear IWV Internal Water Vapor AEC-Q101 Revision D Check of specification (for raw material only) External Visual Parametric Verification HTRB High Temp. Rev. Bias HTGB High Temp. Gate Bias Temperature Cycle Autoclave H 3 TRB H3TRB HAST High. Accel. Stress Test Intermittent Oper. Life ESD ESD Characterization DPA Destruct. Phy. Analysis Physical Dimensions Terminal Strength RTS Resistance to Solvents Constant Acceleration VVF Vibration Variable Frequency Mechanical Shock HER Hermeticity RSH Resist. to Solder Heat Solderability Thermal Resistance WBS Wire Bond Strength Wire Bond Shear Die Shear Unclamp.Induct.Switch Dielectric Integrity Notes / Remarks Whisker test (IEC 60068-T2-82, JEDEC JESD201) Parameter-Analysis: Comparison of current with changed device characterization, electrical distribution Remarks X SEM-PA-08 P P C Q - - - - - - - - - - - - - - - M - - V - - H - - - - - - - - - - - - - - - - - - - - - - - X SEM-PA-11 Change of mold compound P P Change of mold compound. B - M - - - - U - - - - - - - - - - - - W L - - - - - - - B - - - H - - - - A,F,G - X SEM-PA-13 Change of product marking I P Marking on device. B - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - X SEM-PA-14 -- P A - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - X SEM-PA-18 Move of all or part of assembly to a different location/site/subcontractor. P P Assembly transfer or relocation Dual source strategy C M - - T U - - - - - - - - - - - - L H - - H H - - - H H - - - A,G,I,S,X - Tests, which should be considered for the appropriate process change. A - - M,Q - T U - - - - - - - - - - V W L H - - H H - - - - - H H - A,F,G,I,S,X - Tests, which should be considered for the appropriate process change after selection of condition table. - - M,Q - T U - - - - - - - - - - V W L H - - H H - - - - - H H - A,F,G,I,S,X - Suppliers performed tests (mark with an 'X' for done or 'G' for generic) X X X X X X X X X X X X X Reason for exception of tests: -- Not required. P Information Note required. PCN required. A letter or " " indicates that performance of that stress test should be considered for the appropriate process change. CONDITIONS A B C D E F G H J K L M N P Q S T U V W Only for peripheral routing For symbol rework, new cure time, temp If bond to leadfinger Design rule change Thickness only MEMS element only Only from non-100% burned-in parts Hermetic only EPROM or EEPROM Passivation only Lead free For devices requiring PTC Passivation and gate oxide Passivation and interlevel dielectric Wire diameter decrease Required for plastic SMD only Only for Solder Ball SMD Only for through-hole devices Only for smart power devices For devices with memory sizes 1Mbit SRAM or DRAM => Please mark 'NO' with 'x', default is 'YES' Comments

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