Power Distribution Status and Challenges

Greetings from Georgia Institute of Institute Technology of Technology Power Distribution Status and Challenges Presented by Madhavan Swaminathan Packaging Research Center School of Electrical and Computer Engineering

Acknowledgement Prof. Joungho Kim KAIST, S. Korea Dr. Istvan Novak SUN, USA Mr. James Libous IBM, USA

Introduction Outline Digital Systems - On-Chip - Package and Board - New Technologies Modeling - On-Chip - Package and Board Mixed Signal Systems - RF and Digital Integration Summary

Microprocessor Projections μp 140 mm 2 425 W 70 GB/s 8 GHz

Device Leakage Power Density Increasing Courtesy: J. Libous, IBM - In the past, CMOS active power was main concern with power delivery - As CMOS scales to below 90nm, process related device leakage current contributes a significant passive power component -Leakage current can be reduced by using high-k dielectric materials as replacement for silicon dioxide as the gate dielectric -Passive power puts a further strain on the on-chip power distribution system as it erodes the dc IR drop noise budget and compounds the EM problem

FMAX (MHz) 825 785 745 705 50MHz Increase In FMAX Importance of Power Distribution +/- 100mV +/- 50mV Reliability Wall 665 625 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 Courtesy: Intel VCC (V)

Power Distribution in Heterogeneous Systems A Major Challenge Wire Bond Excitation of Edge Radiation Decoupling Capacitor Memory Die Sensor Die Signal Line RF Die Digital Processor Die GND PWR Signal Via P/G Via SSN Coupling to Power/Ground Via SSN Generation SSN Coupling to Signal/Clock Via

Power Distribution DC to Daylight Problem Package & Board Chip Board and Package Power Distribution Chip Power Distribution VRM Decoupling Capacitors Planes Orthogonal Wiring Low to Medium Frequency High Frequency Chip Package Co-design of Power Distribution is a necessity for Future Systems

Digital Systems

Power Supply Sensitivity - Scaling reduces Vdd headroom (operating on a steeper part of the delay versus Vdd curve) -As Vdd values drop and power densities increase, IR drop becomes more of an issue -Instantaneous voltage drop and spatial variation must be analyzed and controlled -On-chip decoupling capacitors used as local power source to handle instantaneous current demands -Dcaps must be placed where needed and requires a thorough understanding of chip current demand prior to chip physical design Courtesy: J. Libous, IBM

Legacy I/O Voltages Must Be Distributed along with Core Voltages Courtesy: J. Libous, IBM

Voltage Islands and Power Domains Design approach to manage the active and passive power problem Voltage Islands - Areas on chip supplied through separate, dedicated power feed Power Domains Areas within an island fed by same Vdd source but independently controlled via intra-island header switches Distribution Challenges dcap isolation, transients due to activation & deactivation of islands, multiple supplies Simple Concepts.. Complex methodology and design tools Courtesy: J. Libous, IBM

Target Impedance of Power Distribution Network P/G Impedance Skin effect, dielectric, radiation loss Inductive Impedance Target Impedance Ideal Impedance khz MHz GHz THz Frequency [log] A concept becoming popular in the packaging community Courtesy: J. Kim, KAIST

Package on Board 40 mm x 40mm 10 mm x 10mm 25um 25um 25um 25um TSM V1 R1 G1 40um 40um 40um 400um VRM Capacitors 25um 25um 25um 25um 1 mm Capacitors V2 R2 G2 BSM 40um 40um 40um Capacitors 25um 25um 25um 25um er=4 V1 200um G1 200um V2 200um G2 100 mm x 100 mm

Impedance seen by Chip on Package With Capacitors Chip Package Resonance No onchip Cap Onchip=150nF Package and Board Decoupling Chip Decoupling Modeling Results

DC-DC Converters State of the Art 12x10mm 15A POL converter. Source: www.power-one.com SI parameters: POL converter in PC Z out, Z in, V out /V in Output ripple Loop stability Large-signal response Courtesy: I. Novak. SUN

Potential Low-Frequency Problem: Peaky/Changing Output Impedance 1.E+00 Impedance magnitude [ohm] 1.E-01 1.E-02 OFF 4V_0A 4V_1A 4V_2A 4V_3A 4V_5A 4V_7A5 4V_10A 1.E-03 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Frequency [Hz] Courtesy: I. Novak. SUN

Bypass Capacitors State of the Art, Bulk Capacitors Face-down, low-inductance, low-esr, low-profile, D-size polymer tantalum capacitor (curves A on the impedance plot) 1.E-1 Impedance magnitude, inductance [ohm, H] B A B 3.0E-9 2.5E-9 2.0E-9 1.E-2 1.5E-9 Magnitude A Inductance 1.0E-9 5.0E-10 Frequency [Hz] 1.E-3 0.0E+0 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 Overview of Some Options to Create Low-Q Controlled-ESR Bypass Capacitors, Proceedings of EPEP2004, October 25-27, 2004, Portland, OR Courtesy: I. Novak. SUN

Bypass Capacitors State of the Art, Two-terminal Ceramic Capacitors 1210 100uF 0508 4.7uF reverse geometry Impedance magnitude and phase [ohm, deg] Impedance magnitude and phase [ohm, deg] 1.E+02 1.0E+02 8.0E+01 1.E+01 6.0E+01 4.0E+01 1.E+00 2.0E+01 0.0E+00 1.E-01-2.0E+01-4.0E+01 1.E-02-6.0E+01-8.0E+01 1.E-03-1.0E+02 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Frequency [Hz] Courtesy: I. Novak. SUN 1.E+01 1.0E+02 5.0E+01 1.E+00 0.0E+00 1.E-01-5.0E+01 1.E-02-1.0E+02 1.E-03-1.5E+02 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 Frequency [Hz]

Bypass Capacitors Multi-terminal terminal Ceramic and Film Capacitors Multi-terminal capacitor Film capacitor 10-mm long film capacitor 60 mils BGA capacitor 1.E+0 0603 pads Impadance magnitude of 603-10mm film cap. [ohm] 603-size capacitor 1.E-1 Source: AVX Corporation: Low Inductance Capacitors, S-LICC5M396-C brochure Courtesy: I. Novak. SUN 1.E-2 1.E-3 603 pads, end position 0.048 ohm 603 pads, mid position 0.016 ohm Via array 0.0047 ohm 1.E+6 Frequency [Hz] 1.E+7 1.E+8

New Technologies

Plane Resonance and Edge Radiation I Return Current Ground Plane I - V + M S P/G Plane Edge Radiation Power Plane I Courtesy: J. Kim, KAIST

PCB Edge Radiation excited by 500 MHz Clock Edge Radiation (SA-PPG) [dbm] 0-10 -30-50 -70 TV2 SA Measurement TV2 P/G Plane Impedance 1478 3 rd 500 MHz CLK TV2 (7cm,7cm) 100 10 1 0.1 0.01 P/G Plane Impedance [Ω] 14cm 0 0.5 1 1.5 2 2.5 3 Short Via Courtesy: J. Kim, KAIST Frequency [GHz] 14cm

Thin Film Embedded Capacitor Vehicle Code Dielectric Thickness Dielectric Constant (DK) Capacitance/cm 2 Total Capacitance (5cm x 5cm with 2 pairs) A 50 μm 4.6 81.46 pf 4.07 nf B 25 μm 4.6 162.91 pf 8.15 nf C 12 μm 4.6 339.40 pf 16.97 nf D 10 μm 16 1416.64 pf 70.83 nf E 10 μm 25 2213.50 pf 110.68 nf 50μm 25μm 12μm A with x50 Courtesy: J. Kim, KAIST A with x100 A with x500 B with x500 C with x500

Measured PDN Impedance Curve Power/Ground Impedance [db ohm] 30 20 10 0-10 -20-30 -40-50 16 x 100nF Discrete Capacitors With Thin Film Embedded Capacitor (Thickness : 12μm, DK : 4.6) C With Thin Film Embedded Capacitor (Thickness : 10μm, DK : 25) E Improvement at low frequency range with High-DK Embedded Material TM02/20 Mode Resonance (5cm x 5cm) 1 10 100 1000 3000 Frequency [MHz] Significant Improvement over GHz With Thin Film Embedded Capacitor Significant improvement over GHz with Thin Film Embedded Capacitor (Very low ESL of Embedded Capacitor) More improvement at low frequency range with high-dk embedded capacitor (More Capacitance) Courtesy: J. Kim, KAIST

Low ESL Embedded Decoupling Capacitors in the Package Total Bump Inductance 6 fh Negligible Loop inductance for charge transfer Dielectric thickness of 0.1um leads to ph spreading inductance 10 GHz Microprocessor (Bare die) 50um balls on 100um pitch Digital ICs (µp, Memory) L=27pH per Vdd Gnd ball Low CTE, High Modulus Composite Substrate Zero signal delay penalty Embedded decoupling 1 3μF/cm 2 charge reservoir

Technical Innovation in Embedded Capacitors Low temperature hydrothermal synthesis of BaTiO 3 <100 C Process Temperature 100-500nm Thick Film Capacitance Density > 1µF/cm 2 Achieved Loss Tangent ~ 0.05 Sol-gel synthesis of BaTiO 3, SrTiO 3 High Temperature Process (~600 C) Rapid Thermal Process Developed (3 min) 200-900nm Films Processed on Ni/Ti Foils Lamination Process for Integration Capacitance Density ~500nF/cm 2 Loss Tangent ~0.005 450 0.3 400 Dielectric Constant 350 300 250 200 0.2 0.1 Loss Tangent 150 100 2 3 4 6 7 Frequency (GHz) High frequency measurement 0

Modeling

On-chip Power Distribution Network Cross section of ASIC power distribution* 3D view of on-chip power grid

Finite Difference Time Domain Method Z Y = R = G dc dc + + jϖl jϖc ext ext + 1+ + 1+ jϖl1 jϖl / R 1 jϖc jϖc 1 1 1 / G 1, SiO2 hox Si hsi Gnd First order Debye equivalent circuit Cross section of on-chip power grid

Simulation of Power Supply Noise using FDTD Chip composed of blocks with different power densities (unit=mw/mm 2 ) Size(mm mm) Metal Layers Nodes Element (RLGC) 6 6 6 (M1 M6) 5,661,354 22,645,380

Modeling of Core Power Distribution in Package and Board Unit cell size: 0.093 X 0.093 cm * Port 1: ( 0.677, 3.7268) Port 2: ( 1.058, 1.3138) Port 3: ( 3.471, 1.6948) Port 4: ( 3.09, 4.1078) cm Decaps Δ Ferrite + C25 Original Plane Grid Courtesy: Kodak

Modeling of Multi-layered Planes in Packages and Boards using Transmission Matrix Method Horizontal plane pair approximated using discretized RLGC parameters Matrix Reduction Planes connected using via inductance

Model to Hardware Correlation Z11 Blue: Measurement Red: T Matrix Bare Board for 1V8 Plane

Modeling of I/O Power Distribution 3. Non-linear Macro-models Of drivers Port 2 Port 1 0.6 V (Vdd) Gnd 1. Macro-models of PDN Port 3 PDN Macro-model 0.3 V (Vterm) 50 Ω Differential Driver Gnd Gnd 50 Ω 50 Ω Differential Transmission Lines (50 Ω) 2. RLGC Models or Macro-models of Transmission Lines

Coupled Signal and Power Distribution Simulation using TMM

Test Case: IBM HSTL_B 350MHz Driver port2 port4 (V dd = 1.5 V) port5 port1 port3 10 drivers V(port1) V(port2) g2 2 1.5 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 2 x 10-8 1.5 g1 V_ne(t) VDD transmission line 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 2 Time g4 GND g5 V_fe(t) 1 pf g3 Simulation time in (sec) 8000 7000 6000 5000 4000 3000 2000 1000 0 Blue HSTL model Red Macro-model 0 5 10 15 20 25 30 35 Number of drivers switching Time (s) 100X Speed-up

[Top View] Example from SUN [Cross Section] 195 Core Decoupling Capacitor SRAM 274 Interconnects 750 MHz Microprocessor Interconnects Interconnects Gnd Core Vdd Gnd I/O Vdd Gnd I/O Vdd Interconnects y 128 Interconnects Connector Interconnects Gnd I/O Vdd Gnd x 178 I/O Decoupling Capacitor

[Frequency Domain] I/O PDS Noise [Time Domain] 0 1.53 4 nsec (250 MHz) -10 1.52 8 nsec (125 MHz) -20 Noise Power (db) -30-40 -50 125 MHz (Connector Bus) 250 MHz (SRAM Bus) 750 MHz 1500 MHz Volts Noise 1.51 1.5 1.49-60 1.48-70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (MHz) 1.47 0 5 10 15 20 25 30 35 40 45 50 Time (nsec) Simulation Time: 124 Seconds with 20 ps time step Blue: Measurements, Red: Modeling I/O switching noise is caused by the return current flowing on the I/O vdd/gnd planes.

Heterogeneous Systems

Heterogeneous Integration Digital-Analog Coupling f1 f2 Multiband antenna Multiband filter Multiband Balun Multiband Low Noise Amplifier Multiband Differential Downconverter ADC + Processor Multiple Signal Generator PACKAGE DOMAIN CHIP DOMAIN Example: 802.11 a/b/g; WiMaX; UWB; Handset

Electromagnetic Coupling in Mixed-Signal Systems Digital circuit GND layer Current EM wave Load RF circuit VDD layer Dielectric layer (ε r = 4.4) EM coupling

Isolation Methods Available Split planes & Ferrite bead - ferrite bead is placed between split planes for DC connection - require a single power supply - still poor isolation at high frequencies due to EM coupling through a gap Power-plane Segmentation - conducting neck is placed between split planes for DC connection - requires a single power supply - poor isolation except narrow frequency range Better isolation technique is needed for mixed-signal system applications

EBG Structure Two-dimensional (2-D) square lattice with each element consisting of a metal patch with two connecting metal branches. Metal branches introduce additional inductance and capacitance is mainly formed by metal patches and corresponding parts of other plane. Distributed LC network. Schematic of Novel EBG Structure in GND plane Unit Cell of Novel EBG Structure

Noise Isolation using Electronic Bandgap Structures Substrate Coupling 300MHz FPGA with 2.13GHz LNA Patterned Ground Plane EBG Response

Noise Reduction with EBG Structure -65-70 7 th harmonic noise peak at LNA output for mixed-signal system without AI-EBG structure Power (dbm) -75-80 -85 7 th harmonic noise peak at LNA output for mixed-signal system with AI-EBG structure -90 2.09E+09 2.10E+09 2.10E+09 2.10E+09 2.10E+09 2.10E+09 2.11E+09 Frequency (Hz)

Digital Systems Modeling Increasing chip power and technology scaling placing challenges on IR drop, EM, leakage and active power Voltage islands on-chip and multiple I/O voltages making the design complex Decoupling capacitors on package running out of steam Embedding decoupling increasing design complexity On-chip Modeling: Still very complex due to the feature sizes, irregular layouts and uncertainty in the return current path Chip Package Interface: Integrated modeling of chip and package still doesn t exist Estimation of current signature a big challenge Modeling of isolation in mixed signal systems with low noise floors Heterogeneous Integration Summary Achieving -85dBm over broad frequency a challenge 3D Integration is making it worse

Reference M. Swaminathan, J. Kim, I. Novak and J. Libous, Power Distribution Networks for System on a Package: Status And Challenges, IEEE Trans. On Advanced Packaging, pp. 286 300, Vol. 27, No. 2, May 2004