July 5, 2005 Toshiba TH58NVG2S3BTG00 4 Gbit NAND Flash Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Table of Contents Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Device Identification 2.1 Package 2.2 Die 2.3 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Low-Voltage Transistors and Poly 3.7 Peripheral High-Voltage Transistors and Poly 3.8 Flash Array Transistors and Poly 3.9 Isolation 3.10 Wells and Substrate 4 Memory Cell Analysis 4.1 Plan-View Analysis 4.2 Cross-Sectional Analysis Parallel to Bit Line 4.3 Cross-Sectional Analysis Parallel to Word Line 5 Materials Analysis 5.1 TEM-EDS Analysis
Table of Contents 6 Critical Dimensions 6.1 Package and Die 6.2 Horizontal Dimensions 6.3 Vertical Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Identification 2.1.1 Apple ipod Shuffle 2.1.2 820-1715A ipod Board 2.1.3 Top Package Photograph 2.1.4 Bottom Package Photograph 2.1.5 Plan-View Package X-Ray 2.1.6 Side-View Package X-Ray 2.2.1 Die Photograph 2.2.2 Die Markings 2.3.1 Die Corner A 2.3.2 Die Corner B 2.3.3 Die Corner C 2.3.4 Die Corner D 2.3.5 Typical Bond Pads 2.3.6 Minimum Pitch Bond Pads 2.3.7 Small Bond Pad Detail 2.3.8 Small Bond Pad Detail 2.3.9 Between Memory Blocks 2.3.10 Peripheral Circuitry 3 Process Analysis 3.1.1 General Device Structure in Memory Array 3.1.2 General Device Structure in Peripheral Area 3.1.3 Die Edge 3.1.4 Die Seal Structure 3.2.1 Bond Pad Over-view 3.2.2 Bond Pad - Edge 3.3.1 General Dielectric Structure 3.3.2 Passivation 3.3.3 Passivation Nitride TEM 3.3.4 IMD 2 and IMD 1 3.3.5 IMD 1 TEM 3.3.6 IMD, PMD and STI 3.3.7 PMD and STI 3.3.8 PMD TEM
Overview 1-2 3.4.1 Minimum Pitch Metal 3 3.4.2 Metal 3 TiN/Ti Barrier TEM 3.4.3 Minimum Pitch Metal 2 3.4.4 Minimum Pitch Metal 2 TEM 3.4.5 Metal 2 Lengthwise TEM 3.4.6 Metal 2 Barrier TEM 3.4.7 Minimum Pitch Metal 1 Plan-View 3.4.8 Metal 1 3.4.9 Metal 1 TEM 3.4.10 Metal 1 Barrier TEM 3.5.1 Minimum Pitch Via 2s 3.5.2 Minimum Pitch Via 1 and Contacts 3.5.3 Minimum Pitch Contact to Polycide 3.5.4 Via 1 TEM 3.5.5 Self-Aligned Poly 4 Bit Line Contact 3.5.6 Self-Aligned Poly 4 Contact TEM 3.5.7 Self-Aligned Poly 4 Bit Line Contact Top TEM 3.5.8 Poly 4 HVMOS Contact to Substrate 3.5.9 Poly 4 HVMOS Contact to Substrate TEM 3.5.10 Poly 4 HVMOS Contact to Substrate Detail 3.5.11 Poly 4 HVMOS Contact to Substrate Bottom 3.6.1 Peripheral NMOS Transistor 3.6.2 Minimum Gate Length/Minimum Pitch Peripheral NMOS Transistors 3.6.3 Minimum Gate Length Peripheral PMOS Transistor 3.6.4 Minimum Pitch Peripheral PMOS Transistors 3.6.5 Minimum Space Poly (Glass Etch) 3.7.1 HVMOS Word Line Driver Transistors Plan-View 3.7.2 HVMOS Word Line Driver Transistors Plan-View Detail 3.7.3 HVNMOS Transistor (Glass Etch) 3.7.4 HVMOS Transistor Detail (Glass Etch) 3.7.5 HVMOS Transistor TEM 3.7.6 HVMOS Transistor Detail TEM 3.7.7 HVMOS Transistor Gate Oxide TEM 3.8.1 Flash Memory Transistors Plan-View 3.8.2 Floating Gate Transistors (Bit Line Cross-Section, Glass Etch) 3.8.3 Floating Gate Transistors (Bit Line Cross-Section) TEM 3.8.4 Floating Gate Transistors Detail (Bit Line Cross-Section) TEM
Overview 1-3 3.8.5 Floating Gate Transistors ONO Inter-Poly Dielectric (Bit Line Cross-Section) TEM 3.8.6 Floating Gate Transistors (Word Line Cross-Section) 3.8.7 Floating Gate Transistors (Word Line Cross-Section) TEM 3.8.8 Floating Gate Transistors ONO Inter-Poly Dielectric (Word Line Cross-Section) TEM 3.8.9 Floating Gate Transistor Gate Oxide TEM 3.8.10 Ground Select Transistors (Bit Line Cross-Section) 3.8.11 Bit Line Select Transistors (Bit Line Cross-Section, Glass Etch) 3.8.12 Bit Line Select Transistor (Bit Line Cross-Section) TEM 3.8.13 Select Transistor Detail (Bit Line Cross-Section) TEM 3.9.1 Gate Poly Over STI 3.9.2 Minimum Width STI 3.9.3 Gate Poly Over STI TEM 3.10.1 Array Wells SCM 3.10.2 SRP Profile of Array Well Structure 3.10.3 SRP Profile of Periphery P-Well 3.10.4 SRP Profile of Periphery N-Well 4 Memory Cell Analysis 4.1.1 Annotated Die Photograph 4.1.2 Memory Array Corner Optical Plan-View 4.1.3 Memory Array Edge Detail Optical Plan-View 4.1.4 Memory Array at Metal 3 (6K) 4.1.5 Memory Array at Metal 2 Bit Lines and V SS (6K) 4.1.6 Memory Array at Metal 2 Bit Lines, V SS and Erase Line (6K) 4.1.7 Memory Array at Metal 2 Bit Lines Detail (60K) 4.1.8 Memory Array at Metal 1 SSL and GSL Contacts (6K) 4.1.9 Memory Array at Metal 1 Erase and GSL Contacts (6K) 4.1.10 Memory Array at Metal 1 Erase and GSL Contacts (10K) 4.1.11 Metal 1 Bit Line Local Interconnects (30K) 4.1.12 Memory Array at Poly Word Lines (6k) 4.1.13 Memory Array at Poly Word Lines (10k) 4.1.14 Memory Array at Poly Word Lines SSL Contact (30k) 4.1.15 Memory Array at Poly Word Lines GSL Contact (30k) 4.1.16 Poly Word Lines Detail (60k) 4.1.17 Memory Array at Poly Floating Gates Detail (60k)
Overview 1-4 4.1.18 Memory Array at Substrate Edge (6K) 4.1.19 Memory Array at Substrate (60K) 4.2.1 Memory Array (Bit Line Cross-Section) 4.2.2 Memory Array (Bit Line Cross-Section) 4.2.3 Bit Line Contact and SSL Transistor (Bit Line Cross-Section) 4.2.4 V SS Contact and GSL Transistor (Bit Line Cross-Section) 4.2.5 Floating Gate Transistors (Bit Line Cross-Section) 4.2.6 Erase Line Substrate Contact (Bit Line Cross-Section) 4.3.1 Memory Array (Word Line Cross-Section) 4.3.2 Memory Array V SS Bus Lines (Word Line Cross-Section) 4.3.3 Bit Lines (Word Line Cross-Section) 4.3.4 Word Lines and Floating Gate Transistors (Word Line Cross-Section) 5 Materials Analysis 5.1.1 EDS Analysis Locations Over-View 5.1.2 EDS Analysis Locations PMD Detail 5.1.3 EDS Spectrum of Passivation 3 Nitride 5.1.4 EDS Spectrum of Passivation 2 Oxide 5.1.5 EDS Spectrum of IMD 2-2 Oxide 5.1.6 EDS Spectrum of IMD 2-1 Oxide 5.1.7 EDS Spectrum of IMD 1 Oxide 5.1.8 EDS Spectrum of PMD 4 Oxide 5.1.9 EDS Spectrum of PMD 3 Oxide 5.1.10 EDS Spectrum of PMD-2 BPSG 5.1.11 EDS Spectrum of Gate Cap Nitride 5.1.12 EDS Spectrum of Poly 2 Gate Tungsten Silicide
Overview 1-5 1.2 List of Tables 1.5.1 Device Summary 1.6.1 Summary of Major Process Findings 2.1.1 Decoded TH58NVG2S3BTG00 Part Number 2.1.2 Probable Specifications 2.3.1 Package and Die Dimensions 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.6.1 Peripheral Transistor and Polysilicon Horizontal Dimensions 3.6.2 Peripheral Transistor and Poly Vertical Dimensions 3.7.1 HVMOS Transistors Horizontal Dimensions 3.7.2 HVMOS Transistors Vertical Dimensions 3.8.1 Flash Memory Array Transistors Horizontal Dimensions 3.8.2 Flash Memory Array Transistors Vertical Dimensions 3.9.1 Minimum Horizontal STI Dimensions 3.10.1 Summary of Wells Vertical Dimensions 5.1.1 Summary of Dielectric Composition
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