Power MOSFET PRODUCT SUMMARY (V) 900 R DS(on) ( ) V GS = 10 V 3.7 Q g (Max.) (nc) 78 Q gs (nc) 10 Q gd (nc) 42 Configuration Single D D 2 PAK (TO263) G G D S ORDERING INFORMATION Package Lead (Pb)free and Halogenfree Lead (Pb)free S NChannel MOSFET FEATURES Halogenfree According to IEC 61249221 Definition Dynamic dv/dt Rating Repetitive Avalanche Rated Fast Switching Ease of Paralleling Simple Drive Requirements Compliant to RoHS Directive 2002/95/EC DESCRIPTION Third generation MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low onresistance and costeffectiveness. The D 2 PAK (TO263) package is universially preferred for all commercialindustrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the D 2 PAK (TO263) contribute to its wide acceptance throughout the industry. D 2 PAK (TO263) SiHFBF30SGE3 IRFBF30SPbF SiHFBF30SE3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 900 V GateSource Voltage V GS ± 20 Continuous Drain Current V GS at 10 V T C = 25 C 3.6 I D T C = 100 C 2.3 A Pulsed Drain Current a I DM 14 Linear Derating Factor 1.0 W/ C Single Pulse Avalanche Energy b E AS 250 mj Repetitive Avalanche Current a I AR 3.6 A Repetitive Avalanche Energy a E AR 13 mj Maximum Power Dissipation T C = 25 C P D 125 W Peak Diode Recovery dv/dt c dv/dt 1.5 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 150 Soldering Recommendations (Peak Temperature) for 10 s 300 d C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V DD = 50 V, starting T J = 25 C, L = 36 mh, R g = 25, I AS = 3.6 A (see fig. 12). c. I SD 3.6 A, di/dt 70 A/μs, V DD 600, T J 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91389 www.vishay.com S111055Rev. C, 30May11 1
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 62 Maximum JunctiontoAmbient (PCB Mount) a R thja 40 C/W Maximum JunctiontoCase (Drain) R thjc 1.0 Note a. When mounted on 1" square PCB (FR4 or G10 material). SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage V GS = 0, I D = 250 μa 900 V Temperature Coefficient /T J Reference to 25 C, I D = 1 ma 1.1 V/ C GateSource Threshold Voltage V GS(th) = V GS, I D = 250 μa 2.0 4.0 V GateSource Leakage I GSS V GS = ± 20 V ± 100 na = 900 V, V GS = 0 V 100 Zero Gate Voltage Drain Current I DSS = 720 V, V GS = 0 V, T J = 125 C 500 μa DrainSource OnState Resistance R DS(on) V GS = 10 V I D = 2.2 A b 3.7 Forward Transconductance g fs = 100 V, I D = 2.2 A b 2.3 S Dynamic Input Capacitance C iss V GS = 0 V, 1200 Output Capacitance C oss = 25 V, 320 pf Reverse Transfer Capacitance C rss f = 1.0 MHz, see fig. 5 200 Total Gate Charge Q g 78 GateSource Charge Q gs I V GS = 10 V D = 3.6 A, = 360 V, see fig. 6 and 13 b 10 nc GateDrain Charge Q gd 42 TurnOn Delay Time t d(on) 14 Rise Time t r V DD = 450 V, I D = 3.6 A, 25 TurnOff Delay Time t d(off) R g = 12, R D = 120, see fig. 10 b 90 ns Fall Time t f 30 Between lead, Internal Drain Inductance L D 6 mm (0.25") from 4.5 D package and center of nh G Internal Source Inductance L S die contact 7.5 DrainSource Body Diode Characteristics S Continuous SourceDrain Diode Current I MOSFET symbol D S 3.6 showing the integral reverse G Pulsed Diode Forward Current a I SM p n junction diode S 14 A Body Diode Voltage V SD T J = 25 C, I S = 3.6 A, V GS = 0 V b 1.8 V Body Diode Reverse t rr 430 650 ns Recovery Time T J = 25 C, I F = 3.6 A, di/dt = 100 A/μs b Body Diode Reverse Recovery Charge Q rr 1.4 2.1 μc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. www.vishay.com Document Number: 91389 2 S111055Rev. C, 30May11
TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) Fig. 1 Typical Output Characteristics, T C = 25 C Fig. 3 Typical Transfer Characteristics Fig. 2 Typical Output Characteristics, T C = 150 C Fig. 4 Normalized OnResistance vs. Temperature Document Number: 91389 www.vishay.com S111055Rev. C, 30May11 3
Fig. 5 Typical Capacitance vs. DraintoSource Voltage Fig. 7 Typical SourceDrain Diode Forward Voltage Fig. 6 Typical Gate Charge vs. GatetoSource Voltage Fig. 8 Maximum Safe Operating Area www.vishay.com Document Number: 91389 4 S111055Rev. C, 30May11
R D R g V GS D.U.T. V DD 10 V Pulse width 1 µs Duty factor 0.1 % Fig. 10a Switching Time Test Circuit 90 % 10 % V GS t d(on) t r t d(off) t f Fig. 9 Maximum Drain Current vs. Case Temperature Fig. 10b Switching Time Waveforms Fig. 11 Maximum Effective Transient Thermal Impedance, JunctiontoCase Vary t p to obtain required I AS R g L D.U.T I AS V DD A t p V DD 10 V t p 0.01 Ω I AS Fig. 12a Unclamped Inductive Test Circuit Fig. 12b Unclamped Inductive Waveforms Document Number: 91389 www.vishay.com S111055Rev. C, 30May11 5
Fig. 12c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 10 V Q G 12 V 0.2 µf 50 kω 0.3 µf Q GS Q GD D.U.T. V DS V G V GS Charge Fig. 13a Basic Gate Charge Waveform 3 ma Fig. 13b Gate Charge Test Circuit I G I D Current sampling resistors www.vishay.com Document Number: 91389 6 S111055Rev. C, 30May11
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = 10 V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 9 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91389. Document Number: 91389 www.vishay.com S111055Rev. C, 30May11 7
AN826 RECOMMENDED MINIMUM PADS FOR D 2 PAK: 3Lead 0.420 (10.668) 0.635 (16.129) 0.355 (9.017) 0.145 (3.683) 0.135 (3.429) 0.200 (5.080) 0.050 (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11Apr05 www.vishay.com 1
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