LT High Signal Level Upconverting Mixer FEATURES Wide RF Output Frequency Range to MHz Broadband RF and IF Operation +7dBm Typical Input IP (at 9MHz) +dbm IF Input for db RF Output Compression Integrated LO Buffer: dbm Drive Level Single-Ended or Differential LO Input Double-Balanced Mixer Enable Function Single.V.V Supply Voltage Range -Pin TSSOP Exposed Pad Package APPLICATIO S U CATV Downlink Infrastructure Wireless Infrastructure High Linearity Mixer Applications DESCRIPTIO U The LT mixer is designed to meet the high linearity requirements of cable TV infrastructure downstream transmitters and wireless infrastructure transmit systems. The IC includes a differential LO buffer amplifier driving a double-balanced mixer. The LO, RF and IF ports can be easily matched to a broad range of frequencies for different applications. The high performance capability of the LO buffer allows the use of a single-ended source, thus eliminating the need for an LO balun. The LT mixer delivers +7dBm typical input rd order intercept point at 9MHz, and +.dbm IIP at 9MHz, with IF input signal levels of dbm. The input db compression point is typically +dbm., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO U ENABLE LT EN BIAS VCCLO V RF Output Power and rd Order Intermodulation vs Input Power (Two Input Tones) MOD MHz IF + IF LO INPUT 99MHz dbm LO + BIAS RF + RF LO Fa 9MHz TO DOWNMIXER P OUT, IM (dbm/tone) 7 8 9 P OUT IM P LO = dbm f RF = 9MHz f RF = 99MHz IF INPUT POWER (dbm/tone) Fb Figure. High Signal Level Upmixer for CATV Downlink Infrastructure. i
LT ABSOLUTE AXI U RATI GS (Note ) W W W Supply Voltage....V Enable Voltage....V to +.V LO Input Power (Differential)... dbm IF Input Power (Differential)... dbm IF +, IF DC Currents... ma Operating Temperature Range... C to 8 C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C U U U W PACKAGE/ORDER I FOR ATIO LO IF + IF BIAS 7 8 TOP VIEW LO + LO RF + RF EN 9 FE PACKAGE -LEAD PLASTIC TSSOP T JMAX = C, θ JA = 8 C/W EXPOSED PAD IS GROUND (MUST BE SOLDERED TO PRINTED CIRCUIT BOARD) ORDER PART NUMBER LTEFE FE PART MARKING EFE Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN TYP MAX UNITS = V DC, EN = High, IF Input Frequency Range (Note ) to MHz LO Input Frequency Range (Note ) to 7 MHz RF Output Frequency Range (Note ) to MHz 9MHz Application: (Test Circuit Shown in Figure ) = V DC, EN = High,, IF Input = MHz at dbm, LO Input = GHz at dbm, RF Output Measured at 9MHz, unless otherwise noted. (Notes, ) IF Input Return Loss With External Matching, Z O = Ω db LO Input Power to dbm LO Input Return Loss With External Matching, Z O = Ω db RF Output Return Loss With External Matching, Z O = Ω 7 db Conversion Gain db LO to RF Leakage dbm Input db Compression.9 dbm Input rd Order Intercept Two-Tone, dbm/tone, f = MHz 7 dbm Input nd Order Intercept Single-Tone, dbm dbm SSB Noise Figure db f
LT ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN TYP MAX UNITS.9GHz Application: (Test Circuit Shown in Figure ) = V DC, EN = High,, IF Input = MHz at dbm, LO Input =.9GHz at dbm, RF Output Measured at 9MHz, unless otherwise noted. (Notes, ) IF Input Return Loss With External Matching, Z O = Ω db LO Input Power to dbm LO Input Return Loss With External Matching, Z O = Ω. db RF Output Return Loss With External Matching, Z O = Ω. db Conversion Gain.7 db LO to RF Leakage 7 dbm Input db Compression. dbm Input rd Order Intercept Two-Tone, dbm/tone, f = MHz. dbm Input nd Order Intercept Single-Tone, dbm dbm SSB Noise Figure db Power Supply Requirements: = V DC, EN = High,, unless otherwise noted. Supply Voltage. to. V DC Supply Current ma Shutdown Current (Chip Disabled) EN = Low µa Enable Mode Threshold EN = High V DC Disable Mode Threshold EN = Low. V DC Turn ON Time (Note ) µs Turn OFF Time (Note ) µs Enable Input Current EN = V µa Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : External components on the final test circuit are optimized for operation at f RF = 9MHz, f LO = GHz and f IF = MHz (Figure ). Note : Specifications over the C to 8 C temperature range are assured by design, characterization and correlation with statistical process controls. Note : External components on the final test circuit are optimized for operation at f RF = 9MHz, f LO =.9GHz and f IF = MHz (Figure ). Note : Turn On and Turn Off times are based on rise and fall times of RF output envelope from full power to dbm with an IF input power of dbm. Note : Part can be used over a broader range of operating frequencies. Consult factory for applications assistance. i
LT TYPICAL PERFOR A CE CHARACTERISTICS U W (9MHz Application) = V DC, EN = High,, IF Input = MHz at dbm, LO Input = GHz at dbm, RF Output Measured at 9MHz, unless otherwise noted. For -Tone Measurements: nd IF Input = MHz at dbm. (Test Circuit Shown in Figure ). P OUT, IM (dbm/tone) 7 RF Output Power and rd Order Intermodulation vs IF Input Power (Two Input Tones) IM P OUT POUT, IM (dbm) 7 RF Output Power and nd Order Intermodulation vs IF Input Power (Single Input Tone) IM P OUT Conversion Gain vs IF Input Power (Single Input Tone) 8 IF INPUT POWER (dbm/tone) G 8 IF INPUT POWER (dbm) G IF INPUT POWER (dbm) G Conversion Gain and IIP vs LO Power LO to RF Leakage vs LO Power IIP vs LO Power 8 IIP GAIN 9 7 IIP (dbm) LO TO RF LEAKAGE (dbm) IIP (dbm) LO POWER (dbm) G 9 LO POWER (dbm) G LO POWER (dbm) G Conversion Gain and LO to RF Leakage vs Output Frequency GAIN LO LEAKAGE 8 IF = MHz, LO SWEPT FROM MHz TO MHz AT dbm 7 9 RF OUTPUT FREQUEY (MHz) G7 LO TO RF LEAKAGE (dbm) IIP, IIP (dbm) IIP and IIP vs Output Frequency IIP IIP IF = MHz, LO SWEPT FROM MHz TO MHz AT dbm 7 9 RF OUTPUT FREQUEY (MHz) G8 NOISE FIGURE (db) 8 SSB Noise Figure vs Output Frequency IF = MHz, LO SWEPT FROM MHz TO MHz AT dbm 7 9 RF OUTPUT FREQUEY (MHz) G9 f
TYPICAL PERFOR A CE CHARACTERISTICS U W LT (9MHz Application) = V DC, EN = High,, IF Input = MHz at dbm, LO Input = GHz at dbm, RF Output Measured at 9MHz, unless otherwise noted. For -Tone Measurements: nd IF Input = MHz at dbm. (Test Circuit Shown in Figure ). LO and RF Port Return Loss vs Frequency Conversion Gain vs Supply Voltage IIP and IIP vs Supply Voltage RF PORT IIP RETURN LOSS (db) LO PORT IIP (dbm) IIP IIP (dbm) 7 9 FREQUEY(MHz).....8.... SUPPLY VOLTAGE (V).....8.... SUPPLY VOLTAGE (V) G G G (.9GHz Application) = V DC, EN = High,, IF Input = MHz at dbm, LO Input =.9GHz at dbm, RF Output Measured at 9MHz, unless otherwise noted. For -Tone Measurements: nd IF Input = MHz at dbm. (Test Circuit Shown in Figure ). POUT, IM (dbm/tone) 7 8 RF Output Power and rd Order Intermodulation vs IF Input Power (Two Input Tones) IM P OUT IF INPUT POWER (dbm/tone) P OUT, IM (dbm) 7 8 RF Output Power and nd Order Intermodulation vs IF Input Power (Single Input Tone) P OUT IM IF INPUT POWER (dbm) Conversion Gain vs IF Input Power (Single Input Tone) IF INPUT POWER (dbm) G G G i
LT TYPICAL PERFOR A CE CHARACTERISTICS U W (.9GHz Application) = V DC, EN = High, T A = ºC, IF Input = MHz at dbm, LO Input =.9GHz at dbm. RF Output Measured at 9MHz, unless otherwise noted. For -Tone Measurements: nd IF Input = MHz at dbm. (Test Circuit Shown in Figure ). Conversion Gain and IIP vs LO Input Power IIP GAIN 7 9 IIP (dbm) LO TO RF LEAKAGE (dbm) LO to RF Leakage vs LO Input Power IIP (dbm) IIP vs LO Input Power LO INPUT POWER (dbm) G 7 LO INPUT POWER (dbm) G7 LO INPUT POWER (dbm) G8 Conversion Gain and LO to RF Leakage vs RF Output Frequency GAIN LO LEAKAGE IF = MHz, LO SWEPT 8 FROM MHz TO MHz 7 9 RF OUTPUT FREQUEY (MHz) G9 LO TO RF LEAKAGE (dbm) IIP, IIP (dbm) IIP and IIP vs Output Frequency IIP IIP IF = MHz, LO SWEPT FROM MHz TO MHz 7 9 RF OUTPUT FREQUEY (MHz) G NOISE FIGURE (db) 8 SSB Noise Figure vs Output Frequency IF = MHz, LO SWEPT FROM MHz TO MHz 7 9 RF OUTPUT FREQUEY (MHz) G LO and RF Port Return Loss vs Frequency Conversion Gain vs Supply Voltage IIP and IIP vs Supply Voltage RETURN LOSS (db) LO PORT RF PORT IIP (dbm) IIP IIP IIP (dbm) 7 9 FREQUEY(MHz).....8.... SUPPLY VOLTAGE (V).....8.... SUPPLY VOLTAGE (V) G G G f
LT TYPICAL PERFOR A CE CHARACTERISTICS U W Table. Typical S-Parameters for the IF, RF and LO Ports (referenced to Ω). = V DC, EN = High, T A = ºC. For each Port Measurement, the other Ports are Terminated as Shown in Figure. Frequency Differential IF Port Differential RF Port Differential LO Port Single LO Port (MHz) Mag. Ang. Mag. Ang. Mag. Ang. Mag. Ang.. 79..8 7...8.8..788.. 7....8.8.88..7 7....8..78.. 8....8..789..9.7.9..8.8.779.7.7....8..77.7.9.. 7..8.9.777.9.97.7.9 8..8.8.7 7..8.. 9..8..77 8.9.7...7.798..79..7....797..7.9 7.8....799 7.8.7.7 8.8..7 8..8 8.9.7 8. 9. 7.8...88 9..7 9......8..7..8....87.7.7..7..7..8..7.7.7 7.. 8..8..7.7.7..9.7.8.7.7 7.7...8.9.79..7....7..79 8..77. 7.9.9.7 7.8.789..7 9. 8...7.7.79.9.78. 9...8.8.79.8.78.... 7..79..78.7.9..9..79 7..7 8.. 8...9.79 8..78 9.8... 7..79 9.8.7..7 7....78.8.87..89..9..7.8.8.7.9..8 9..78 8.8. 7. 7.7.7.79 7..7.. 78.7 8...7 7.8.7 8.. 8.9 9. 8.9.8 8..7..8 9..7.. 8..7.9.7 9. i 7
LT PI FU CTIO S U U U LO, LO + (Pins, ): Differential Inputs for the Local Oscillator Signal. They can also be driven single-ended by connecting one to an RF ground through a DC blocking capacitor. For single-ended drive, use LO + for the signal input, as this results in less interference from unwanted coupling of the LO signal to other pins. These pins are internally biased to about.v; thus, DC blocking capacitors are required. An impedance transformation is required to match the LO input to Ω (or 7Ω). At frequencies below.ghz this input can be resistively matched with a shunt resistor. (Pins, 9): Not Connected Internally. Connect to ground for improved isolation between pins. (Pins,, 8,, ): Internal Grounds. These pins are used to improve isolation and are not intended as DC or RF grounds for the IC. Connect these pins to ground for best performance. IF +, IF (Pins, ): Differential Inputs for the IF Signal. A differential signal must be applied to these pins. These pins are internally biased to about.v, and thus require DC blocking capacitors. These pins should be DC isolated from each other for best LO suppression. Imbalances in amplitude or phase between these two signals will degrade the linearity of the mixer. BIAS (Pin 7): Supply Voltage for the LO Buffer Bias and Enable Circuits. This pin should be connected to and have appropriate RF bypass capacitors. Care should be taken to ensure that RF signal leakage to the line is minimized. EN (Pin ): Chip Enable/Disable. When the applied voltage is greater than V, the IC is enabled. When the applied voltage is less than.v, the IC is disabled and the DC current drops to about µa. Under no conditions should the voltage on this pin exceed +.V, even at power on. RF, RF + (Pins, ): Differential Outputs for the RF Output Signal. An impedance transformation may be required to match the outputs. These pins are also used to connect the mixer to the DC supply through impedancematching inductors, RF chokes or transformer center-tap. Care should be taken to ensure that the RF signal leakage to LO and BIAS is minimized. LO (Pin ): Supply Voltage for the LO Buffer Amplifier. This pin should be connected to and have appropriate RF bypass capacitors. Care should be taken to ensure that RF signal leakage to the line is minimized. GROUND (Backside Contact) (Pin 7): DC and RF Ground Return for the Entire IC. This contact must be connected to a low impedance ground plane for proper operation. BLOCK DIAGRA W LO LO + VCCLO IF + LO BUFFER RF + IF BIAS 7 BIAS CIRCUITS 8 7 9 (BACKSIDE) RF EN BD 8 f
LT TEST CIRCUIT LO R C7 C LT LO LO + C C IF C8 x T x C C R C R 7 IF + IF BIAS LO RF + RF EN R L C L EN x T x C C9 C RF C7 8 9 EXPOSED PAD F Component Value Comments C, C9, C, C pf C, C7, C7 pf C.µF C8 pf C, C, C pf C.pF L, L.8nH R Ω R, R 7Ω,.% R kω T : Coilcraft TTWB--A T : M/A-Com ETC.--- Figure. Test Circuit and Evaluation Board Schematic for 9MHz Application. i 9
LT TEST CIRCUIT LO C C7 C LT LO LO + L C C IF C8 x T x C C R C R 7 IF + IF BIAS LO RF + RF EN R L C L EN x T x C L C9 RF C7 8 9 EXPOSED PAD F Component Value Comments C, C9, C, C pf C, C7, C7 pf C.µF C8 pf C, C, C pf C.pF L.8nH L, L.7nH L.8nH R, R 7Ω,.% R kω T : Coilcraft TTWB--A T : M/A-Com ETC.--- Figure. Test Circuit and Evaluation Board Schematic for.9ghz Application. f
LT APPLICATIO S I FOR ATIO U W U U The LT consists of a double-balanced mixer driven by a high-performance, differential, limiting LO buffer. The mixer has been optimized for high linearity and high signal level operation. The LT is intended for applications with LO frequencies of.ghz to.7ghz and IF input frequencies from MHz to MHz, but can be used at other frequencies with excellent results. The LT can be used in applications using either a low side or high side LO. LO Input Port The LO buffer on the LT consists of differential high speed amplifiers and limiters that are designed to drive the mixer quad to achieve high linearity and performance at high IF input signal levels. The LO + and LO pins are the differential inputs to the LO buffer. Though the LO signal can be applied differentially, the LO buffer performs well with only one input driven, thus eliminating the need for a balun. In this case, a capacitor should be connected between the unused LO input pin and ground. The LO pins are biased internally to about.v, and thus must be DC isolated from the external LO signal source. The LO input should be matched to Ω. The impedance match can be accomplished through the use of a reactive impedance matching network. However, for lower LO frequencies (below about.ghz), an easier approach is to use a shunt Ω resistor to resistively match the port. (The resistor must be DC isolated from the LO input pin). This method is broadband and requires LO power levels of only dbm. At higher frequencies, a better match can be realized with reactive components. Transmission lines and parasitics should be considered when designing the matching circuits. Typical S-parameter data for the LO input is included in Table to facilitate the design of the matching network. IF Input Port The IF + and IF pins are the differential inputs to the mixer. These inputs drive the emitters of the switching transistors, and thus have a low impedance. The DC current through these transistors is set by external resistors from each IF pin to ground. The typical internal voltage on the emitters is.v; thus, the current through each IF pin is approximately: I IF =./R IF R IF is the value of the external resistors to ground. Best performance is obtained when the IF inputs are perfectly balanced and.% tolerance resistors are recommended here. The LT has been characterized with 7Ω resistors on each of the IF inputs. The IF signal to the mixer must be differential. To realize this, an RF balun transformer or lumped element balun can be used. The RF transformer is recommended, as it is easier to realize broadband operation, and also does not have the component sensitivity issues of a lumped element balun. The differential input impedance of the IF input is approximately.ω; therefore, a : impedance transformation is required to match to Ω. Selecting a transformer with this impedance ratio will reduce the amount of additional components required, as the full impedance transformation is realized by the transformer. DC-isolating transformers or transmission-line transformers can be used, as could lumped element transformation networks. Because the IF ports are internally biased, they must be DC isolated from the IF source. Additionally, IF + and IF must be DC isolated from each other in order to maintain good LO suppression. i
LT APPLICATIO S I FOR ATIO U W U U On the evaluation board (Figure ), nf DC-blocking capacitors are used on the IF input pins. A pf capacitor on the Ω source side of the input balun is used to tune out the excess inductance to improve the match at MHz. To shift the match higher in frequency, this capacitor value should be reduced. RF Output Port The RF outputs, RF + and RF, are internally connected to the collectors of the mixer switching transistors. These differential output signals should be combined externally through an RF balun transformer or 8 hybrid to achieve optimum performance. These pins are biased at the supply voltage, which can be applied through the center tap of the output transformer. (The center tap should be RF bypassed for best performance). A pair of series inductors can be used to match RF + and RF to the high impedance (Ω) side of a : balun. The output balun has a significant impact on the performance of the mixer. A broadband balun provides better rejection of the f LO spur. If the level of that spur is not critical, a less expensive and smaller balun can be used. The amplitude and phase balances of the balun will affect the LO suppression. (a) Top Layer Silkscreen (b) Top Layer Metal Figure. Evaluation Board Layout. f
LT APPLICATIO S I FOR ATIO U W U U SPECTRUM ANALYZER RF OUT POWER SUPPLY db PAD T E LO SIGNAL GENERATOR LO IN LT IC E DMM T E IF IN SW RF SIGNAL GENERATOR RF SIGNAL GENERATOR + POWER SUPPLY (OR PULSE GENERATOR FOR TURN-ON AND TURN-OFF MEASUREMENTS) F Figure. Test Set-Up for Mixer Measurements i
LT TYPICAL APPLICATIO S U LO C C7 C L LT LO LO + C C IF + (Ω) IF (Ω) C C L C L7 R R IF + IF LO RF + RF TL C TL T C9 RF C8 7 8 BIAS EN 9 R EN EXPOSED PAD F Component Value Comments C, C9 pf C, C7, C8 pf C.µF C pf C, C, C pf C pf L.nH L, L7.nH R, R 7Ω,.% R kω T : MURATA LDBCA Transmission Lines TL, TL Z O = 8Ω L = AT.GHz Figure. Test Circuit Schematic for.ghz RF Application with MHz IF Input Frequency f
TYPICAL APPLICATIO S 7 8 9 U Conversion Gain and LO to RF Leakage vs Output Frequency (Figure ) GAIN f IF = MHz AT 8dBm f IF = MHz AT 8dBm P LO = dbm f LO SWEPT FROM 9MHz TO MHz LO LEAKAGE RF OUTPUT FREQUEY (MHz) 8 Fa 8 8 8 8 8 LO TO RF LEAKAGE ( dbm) IIP, IIP (dbm) IIP and IIP vs Output Frequency (Figure ) IIP f IF = MHz AT 8dBm f IF = MHz AT 8dBm P LO = dbm f LO SWEPT FROM 9MHz TO MHz IIP RF OUTPUT FREQUEY (MHz) Fa LT Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. i
LT PACKAGE DESCRIPTIO U FE Package -Lead Plastic TSSOP (.mm) (Reference LTC DWG # -8-) Exposed Pad Variation BA.7 (.8).9.* (.9.).7 (.8) 9. ±.. ±. SEE NOTE.7 (.8). ±.. ±..7 (.8). BSC. BSC RECOMMENDED SOLDER PAD LAYOUT 7 8..* (.9.77) 8. (.) MAX.9. (..79)..7 (.8.) NOTE:. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS. DIMENSIONS ARE IN (IHES). DRAWING NOT TO SCALE. (.) BSC.9. (.77.8). RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT ILUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.mm (.") PER SIDE.. (..) FE (BA) TSSOP RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT.8GHz to.7ghz Receiver-Front End.8V to.v Supply, Dual-Gain LNA, Mixer, LO Buffer LT MHz Quadrature IF Demodulator with RSSI.8V to.v Supply, 7MHz to MHz IF, 8dB Limiting Gain, 9db RSSI Range LT.GHz to.7ghz Direct IQ Modulator.8V to.v Supply, Four-Step RF Power Control, and Upconverting Mixer MHz Modulation Bandwidth LT 8MHz to.7ghz Measuring Receiver 8dB Dynamic Range, Temperature Compensated,.7V to.v Supply LTC RF Power Detectors with >db Dynamic Range MHz to GHz, Temperature Compensated,.7V to V Supply LT MHz Quadrature Demodulator with VGA.8V to.v Supply, db to 7dB Linear Power Gain LT7 khz to GHz RF Power Detector 8dB Dynamic Range, Temperature Compensated,.7V to V Supply LTC8 MHz to 7GHz RF Power Detector >db Dynamic Range, SC7 Package LT High Signal Level Down Converting Mixer Up to GHz, dbm IIP, Integrated LO Buffer LT/TP K PRINTED IN USA Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9-77 (8) -9 FAX: (8) -7 www.linear.com LINEAR TECHNOLOGY CORPORATION f