Introducing the High Voltage Vertical Technology for High Power Applications Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 1
AGENDA Background Device Overview Packaging Strategy HVVFET Advantages Transistor Performance Reliability Summary Page 2
Silicon Technology History Page 3
Market L-Band (SE Class AB) HVV Breakthrough Product Differentiation 50V Supply Market L-Band (>1000W Devices) HVV 50V Gain Low C GD Path To Higher Operating Voltages & Higher Frequencies MARKETS 75V Supply 100V Supply HVV 75V V BR Low C GS Market L-Band (ANY Power) Markets L-Band (Avionics & Radar) Rugged Power and Efficiency, Low Bandwidth HVV 100V Power Density Low C DS Page 4
Vertical Device Structure Overview Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 5
Vertical Device Structure and Cross Sections Source Metal Gate Metal Thermal Path Gate Poly Source Region Shield Electrode Drain Region Dielectric Platform Epitaxial Layer Planar Breakdown In Epi Region Buried Layer Drain Metal Page 6
Vertical Device Characteristics - BVDSS First Generation Breakdown Voltage Page 7
Vertical Device Current Path Current Flow in Epitaxial Region Page 8
Vertical Device Characteristics Maximum Available Gain 30 25 MAG (db) 20 15 10 5 0 0.5 1 2 5 10 Frequency (GHz) Page 9
Unique Device Characteristics Gate Terminal Bumps Source Terminal Bumps Bump Cross-Section Page 10
High Power Package Overview Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 11
1 Flange with interposer attached Page 12
2A Die attach, AuSn eutectic Page 13
2B Die attach, AuSn eutectic - transparent Page 14
3 Underfill application and cure Page 15
4 Seal leadframe to flange Page 16
5 Output MOSCAP attach Ag epoxy Page 17
6 Input MOSCAP attach Ag epoxy Page 18
7 Wirebond from Interposer to Input MOSCAP 1mil Au wire Page 19
8 Wirebond from Input MOSCAP to Input Lead 1mil Au wire Page 20
9 Wirebond from DIE to Output MOSCAP 1mil Au wire Page 21
10 Wirebond from DIE to Output Lead 1mil Au wire Page 22
11 Completed die and wirebond - closeup Page 23
12 Attach Lid & Mark Page 24
13 Attach Lid & Mark - Array Page 25
Package Types Low cost AlN package for predriver & driver applications (all frequencies) Un-matched HVV planar package for high power, high frequency applications. Matched Page 26
HVVFET Advantages Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 27
High Voltage Advantages High voltage solutions Increases power density Lower current improves reliability Increased output impedance Single power supply Capable of operating at lower voltages (down to 24V) to provide flexibility to the customers. Page 28
High Power Density = Smaller Packages 25W 300W 300W Comparison HVVFET LDMOS High Power in Small Packages SM200 HVVFET is ½ the size Simpler Device for Improved Reliability Page 29
Internal Matching Networks 100W L-Band Radar Device Page 30
Impedance Data 100W L-Band Radar Device Z o = 10 Ω Z IN * Z OUT * 1200MHz 1200MHz Page 31
Design Flexibility Higher Zout Eliminate output Shunt Blocking Cap Flexibility to do external harmonic terminations Improve Doherty Amplifier performance 28V 48V CDS LRes C-blocking CDS Page 32
HVVFET vs Bipolar Solutions Lower System Costs with High Gain & High Power Density Higher gain reduces number of stages High power density packages reduces the PCB area 0912-7 8.5dB, 25% Bipolar 0912-25 8.5dB, 45% Bipolar MDS170L 7dB, 35% Bipolar Four stage Bipolar Lineup MDS350L 8dB, 47% Bipolar Lower number of passive components Single 48V Supply line-up Higher output impedance HVV1011-035 19dB, 48% HVVFET HVV1011-300 16dB, 48% HVVFET Two stage HVVFET Lineup Page 33
Design Example: 600W Live Demo @ MTT-S Positive Gate Bias accomplished through resistive divider network Surface Mount Driver Device 2.5 3.5 All three drains tied to +50V supply 300W Device in HV400 Package (less than half the competitor s package footprint for this power level) PCB footprint of 2.5 X 3.5 with low cost material (er =2.55) Surface Mount Splitter/Combiner Parameter Value Unit Frequency 1090 MHz Output Power 600 Watts Gain 34 db Efficiency 47 % HVV1011-035 20dB, 48% HVVFET HVV1011-300 15dB, 48% HVVFET Page 34
Transistor Performance Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 35
HVVFET Model Performance Good Agreement on DC IV Curves for small device (4W). Modeling Efforts by Page 36
HVVFET Model Performance Modeling Efforts by Page 37
HVVFET Pulsed Performance Duty Cycle Page 38
HVVFET Pulse Response Page 39
Power Swept Performance Typical Power Performance in a Broadband Matched Circuit GAIN (db) 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 GAIN EFFICIENCY 40 50 60 70 80 90 100 110 120 130 140 45 44 43 42 41 40 39 38 37 36 35 ηd (%) Typical Power Performance in a Broadband Matched Circuit OUTPUT POWER (W) OUTPUT POWER (W) 150 135 120 105 90 75 60 45 30 15 0 OUTPUT POWER INPUT RETURN LOSS 0 0.5 1 1.5 2 2.5 3 3.5 0-1 -2-3 -4-5 -6-7 -8-9 -10 IRL (db) INPUT POWER (W) Page 40
Frequency Response Typical Frequency Performance in a Broadband Matched Circuit GAIN (db) 20 19 18 17 16 15 Typical Frequency Performance in a Broadband Matched Circuit GAIN EFFICIENCY 1200 1225 1250 1275 1300 1325 1350 1375 1400 FREQUENCY (MHz) 45 44 43 42 41 40 39 38 37 36 35 ηd (%) OUTPUT POWER (W) 130 129 128 127 126 125 124 123 122 121 120 OUTPUT POWER INPUT RETURN LOSS 1200 1225 1250 1275 1300 1325 1350 1375 1400 FREQUENCY (MHz) 0-2 -4-6 -8-10 -12-14 -16-18 -20 IRL (db) Page 41
Temperature Response Vertical Technology Temperature Stability GAIN (db) 22 21 20 19 18 T CASE 17-40C 16 0C 15 25C 14 85C 13 105C 12 25 50 75 100 125 150 175 200 OUTPUT POWER (W) Page 42
Bias Characterization 1214-100 40V, Gain v Po @ Idq 1214-100 Idq=100mA Gain v Po @ Vdd 23 22 Gain [db] 22.5 22 21.5 21 20.5 20 19.5 19 50mA 100mA 200mA 400mA 500mA Gain [db] 21.5 21 20.5 20 24V 28V 32V 36V 40V 44V 48V 18.5 0 20 40 60 80 100 19.5 0 20 40 60 80 100 120 Po [W] Po [W] 1214-100 40V, Eff v Po @ Idq 1214-100 Idq=100mA Eff v Po @ Vdd 70 70 Eff [%] 60 50 40 30 20 50mA 100mA 200mA 400mA 500mA Eff [%] 60 50 40 30 20 10 24V 28V 32V 36V 40V 44V 48V 10 0 20 40 60 80 100 0 0 20 40 60 80 100 120 Po [W] Po [W] Page 43
Demonstration Circuit Board (100W) Page 44
Mechanical Package Dimensions Page 45
Reliability Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 46
Reliability Report Page 47
Why is Ruggedness Important? Page 48
Output Load Termination VSWR vs Γ 40 35 30 25 VSWR 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Γ 1+ VSWR= 1 Γ Γ Page 49
Typical RF Bench Ruggedness Test Set-up Page 50
Industry s Highest Ruggedness 25 50 24 45 GAIN (db) 23 22 21 20 19 18 Gain Pre-Test Gain Post-Test EFF Pre-Test EFF Post-Test 40 35 30 25 20 15 EFFICIENCY (% 17 10 16 5 15 0 25 50 75 100 125 150 175 200 225 250 275 300 OUTPUT POWER (W) Page 51
Thermal Path enhances device ruggedness Cross Section Of A Transistor Cell Average Drain Current vs VSWR and Phase 10% Overvoltage and 3dB Input Overdrive 18.0 16.0 14.0 ID (ave) [A] 12.0 10.0 8.0 6.0 1:1 5:1 10:1 20:1 2.0 100W HVV Transistor (20 Active Areas) 4.0 0.0-180 -150-120 -90-60 -30 0 30 60 90 120 150 180 Γ Phase [degrees] Page 52
HVVFET vs LDMOS The HVVFET has proven to be extremely rugged and stable allowing the designer to have greater freedom in designing their power amplifier Eliminates the need of heavy isolators and circulators saving space and weight HVV FET Why is the HVVFET so rugged? Suppresses parasitic bipolar transistor present in all MOSFETs Source Metal Nitride Poly LDMOS n+ n p Gate Source Gate Drain n+ n+ n- Source Sinker p Parasitic NPN transistor shorted with source metal Drain Heat in parasitic NPN removed efficiently Page 53
Gold Bonds for Reliable Pulsed Applications Lateral Device with Aluminum Wires Example of an LDMOS product in air cavity package. Red arrow indicates the critical wire loop shapes that may be susceptible to power-cycling induced high-cycle fatigue. Joule heating will cause the bond wires to expand and contract in a cyclical manner, leading to mechanical fatigue HVVi RF pulse testing to ensure consistent operation under stringent conditions HVV1011-300 device pulsed over 1 Billion times per month HVVFET Device with Gold Wires Page 54
Thermal Measurement Techniques Several methods for measuring Rth (jc) or Rth (ja) IR Camera Delta Id Delta Vf Measurements Rth(ja) Thermal resistance junction to air is the only measurement that customers are interested in. Page 55
Traditional Thermal Measurements IR Scan of HVVFET Optotherm IR camera Costly equipment set Thermal Camera and Liquid Nitrogen Page 56
Vertical Device Thermal Measurements TESEC Measurement Equipment Delta Vf Method Not a direct temperature measurement but does represent Max Tj Tj calculated by knowing how Vf of the body diode changes with temperature for a fixed If Can measure transient DC conditions only Can determine Rth junction to air Can derive RC thermal network by recording Vf from various transient conditions Errors of model would be Time delay to acquire a noise free reading Vf v Temperature measurement error Since transient only, it is requires de-embedding of test fixture Page 57
Summary Brian D. Battaglia Applications Engineering HVVi Semiconductors Phoenix, AZ Page 58
HVVFET - Best in Class Si Technology for Avionics & Radar Applications Pulsed Applications HVVFET Bipolar 36V LDMOS 50V LDMOS GaN High Voltage Gain Efficiency (drain) BW Thermal Resistance Ruggedness Power Density System Savings The HVVFET offers: Best in the industry ruggedness (20:1) at least 2x the best in the industry Twice the power in the same package [vs. LDMOS] Significant improvements in gain (5x) and efficiency (30%) [vs. Bipolar] Ease of design due to ruggedness and higher impedances Complete 50V product line that can operate from 5V up to 50V Page 59
Vertical Technology Advantages High Voltage Advantages Lower Current (Reliability) Lower Current (Dissipated Heat) Higher Impedance (Ease of Match) High Breakdown Voltage (Ruggedness) Thermal Advantages Shorter Heat Path (Reliability) Lower Thermal Resistance (Cooler) No Thermal Runaway (Self Regulating) Higher Ruggedness (No Parasitic BJT) System Advantages High Packing Density (smaller package footprint, package savings: cost, size and weight) Reducing Driver Stage Requirement (system level efficiency savings) High Voltage Driver Stage (power supply design savings) Extreme Ruggedness Rating (eliminates isolators reducing cost and weight) Page 60