DESIGN OF RING OSCILLATOR USING CS-CMOS FOR MIXED SIGNAL SOCS

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International Journal of Electrical and Electronics Engineering (IJEEE) ISSN 2278-9944 Vol. 2, Issue 2, May 2013, 21-26 IASET DESIGN OF RING OSCILLATOR USING CS-CMOS FOR MIXED SIGNAL SOCS VINOD KUMAR & R. S. GAMAD Department of Electronics & Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, Mathya Pradesh, India ABSTRACT This paper reports design of a ring oscillator using CS-COMS low noise logic family for mixed signal SOCs. Design has been implemented using 180nm technology with 1.8V supply voltage using CS- CMOS logic. CS-CMOS logic efficiently reduce switching noise while maintaining the speed as compare to the other logics like CSL, CBL etc. After completion of the design authors have simulated the design in Spectre simulator and obtained the best simulation results. Authors have determined the parameters like phase noise, delay. KEYWORDS: Cadence, Current Balanced Logic (CBL), Current Steering CMOS (CS-CMOS), Current Steering Logic (CSL), Mixed Signal SOCs, Ring Oscillator, Spectre Simulator INTRODUCTION Design a ring oscillator circuit in VLSI using CMOS will give high packing density and low power consumption and are easy to design [1],[2]. Most of the power consumed by CMOS gates is due to displacement currents [3] drawn during state-transitions for charging and discharging wire and device capacitances. These increase linearly with the operating frequency and flow through the power supply wires, ground lines, parasitic inductances and capacitances causing ringing and voltage drop. This is the dominant source of substrate noise [4].which causes phase noise in ring oscillator resultant jitter PLL. The problem of switching noise in ring oscillator can be deal by designing a ring oscillator using current steering logic, such as current steering logic (CSL), current-balanced logic (CBL), here present a new logic family called the current-steering CMOS (CS-CMOS) [1] obtained by a simple modification keeping the core CMOS structure intact to preserve its most attractive features. This family not only reduces the switching noise but also delivers higher speed than CSL and CBL for the same power consumption. Designing of ring oscillator using CS-CMOS will give better phase noise compare to CSL and CBL logic. CS-CMOS LOGIC CS-CMOS is obtained by a simple current-steering modification to the standard CMOS family. As in a CMOS inverter, a pair of complimentary transistors connected in series forms the core of the proposed CS-CMOS inverter, as shown in Figure.1. Since CMOS gates do not draw any appreciable current in their static states, constant-current operation requires additional paths for the dc bias current to flow. A pair of complimentary transistors is added in parallel for this purpose. A P-channel transistor sources a constant current to each gate.

22 Vinod Kumar & R. S. Gamad CS-CMOS RING OSCILLATOR Figure 1: Schematic of CS-CMOS Inverter Figure 2: Schematic of CS-CMOS Ring Oscillator

Design of Ring Oscillator Using CS-CMOS for Mixed Signal SOCs 23 SIMULATION RESULTS The design of the low noise family ring oscillator is done using Cadence Tool. The Simulation results are done using Cadence Spectre Environment using UMC 0.18. The Table II shows that the simulated results of the low noise family ring oscillator. The p noise response which shows phase noise at offset frequency 1MHz has shown in figure 3, 4, 5 and Figure 6. Figure 3: Phase Noise of CS-CMOS Ring Oscillator Figure 4: Phase Noise of CSL Ring Oscillator

24 Vinod Kumar & R. S. Gamad Figure 5 Phase Noise of CBL Logic Ring Oscillator Figure 6: Phase Noise of CMOS Ring Oscillator Table 1: Phase Noise at 1 MHZ Offset Frequency and Delay CONCLUSIONS Simulated Results Logic Phase Noise Delay Time CS-CMOS -97.54 dbc/hz 4.2ns CSL -90.47 dbc/hz 8.8ns CBL -65.81 dbc/hz 27.3ns CMOS -64.08 dbc/hz.18ns Design of a low-noise logic CS-CMOS ring oscillator for noise reduction is reported. When it is used in mixed signal integrated systems containing both DSP as well as sensitive analog circuits such as phase-lock loops and data

Design of Ring Oscillator Using CS-CMOS for Mixed Signal SOCs 25 converters in a single chip of silicon. The new family is obtained by a simple current-steering modification to the standard CMOS logic preserving most of the attractive features of CMOS. The well-known constant-current operation enables a substantial reduction of switching noise. Extensive simulations and measurements demonstrate the speed and power advantages of this family over previously proposed logic families namely CSL and CBL. Each gate uses three additional transistors and a capacitor. However, the circuit configuration improves switching speed around the logical ACKNOWLEDGEMENTS This work has been carried out in SMDP VLSI laboratory of the Electronics and Instrumentation Engineering Department of Shri G S Institute of Technology and Science, Indore, India. This SMDP VLSI project is funded by Ministry of Information and Communication Technology, Government of India. Authors are thankful to the Ministry for facilities provided under this project. REFERENCES 1. Ajay Taparia, Member, IEEE, Bhaskar Banerjee, Member, IEEE, and T. R. Viswanathan, Life Fellow, IEEE CS- CMOS: A Low-Noise Logic Family for Mixed Signal SoCs ieee transactions on very large scale integration (vlsi) systems, vol. 19, no. 12, pp. 2141-2148, December 2011. 2. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low Power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473 484, Apr. 1992.. 3. E. Albuquerque et al., A new low-noise logic family for mixed-signal integrated circuits, IEEE Trans.Circuits Syst. I Fundam. Theory Appl.,vol. 46, no. 12, pp. 1498 1500, Dec. 1999. 4. H.-T. Ng and D. J. Allstot, CMOS current steering logic for low voltage mixed-signal circuits, IEEE Trans. Very Large Scale Integrated. (VLSI) Syst., vol. 5, no. 3, pp. 301 308, Sep. 1997 5. Edgar Francisco Monteiro Albuquerque and Manuel Medeiros Silva, Senior Member, IEEE A Comparison by Simulation and by Measurement of the Substrate Noise Generated by CMOS, CSL, and CBL Digital Circuits ieee transactions on circuits and systems: regular papers, vol. 52, no. 4, pp. 734-741 April 2005. 6. D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits, IEEEJ.Solid-StateCircuits,vol.28, no.4, pp.420 430, Apr. 1993. 7. S. Kiaei, S. H. Chee and D. J. Allstot, CMOS source-coupled logic for mixed-mode VLSI in Proc. IEEE Int. Symp. Circuits and Systems, pp. 1608 1611,May 1990. 8. A. Sedra and K. Smith, Microelectronic Circuits (5th edition). Oxford, U.K.: Oxford Univ. Press, 1998. 9. H. C. Yang, L. K. Lee, and R. S. Co, A low jitter 0.3 165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation, IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 582 586, Apr. 1997. 10. J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62 70, Feb. 1989. 11. A. J. van Genderen, N. P. van der Meijs, and T. Smedes, Fast computation of substrate resistances in large circuits, in Proc. Electronic Design and Test Conf. pp. 560 565 Mar. 1996.

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