High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper describes the design of high voltage operational amplifiers in a 0.35µ SOI technology without using special high voltage processes or transistors. Two operational amplifier designs are proposed and characterized based on simulation results. Keywords : op-amp, high voltage, SOI I. Introduction Operational amplifiers (op-amps) are one of the most widely used building blocks in analog circuit design. Recent research efforts have concentrated on the development of low voltage op-amp architectures for low power integrated circuit applications. Very few circuits have been reported for high voltage op-amps which find extensive use in the design of high voltage analog integrated circuits. Most high voltage circuits that have been reported [1] use special processes that can be very expensive or special high voltage transistors in standard processes that make biasing very difficult. This paper presents two op-amp designs that use standard transistors in a standard SOI process using stacked MOSFETs. Motivation: High voltage op-amps are used in the design of many high voltage analog integrated circuits, especially bandgap references [2] that are used in storage circuit design and space applications. Outline: The topologies and their simulation results are presented in sections II and III. Section IV summarizes the paper and discusses future research possibilities. II. The First Op-Amp Topology amp are only about a diode voltage drop and hence, p-channel input transistors are used. R D 1 Figure 1. op-amp based bandgap reference R R ref D2, K Because of the high supply voltage, a stacked MOSFET architecture has been used which is suitable in SOI processes because of the absence of body effect and the potential of reverse biasing the source-drain junction. There are many other advantages of designing high voltage op-amps in SOI processes such as low leakage currents because of the buried oxide layer in SOI devices, low parasitic capacitances, and high speeds. The power dissipation of SOI circuits is also lower than bulk CMOS circuits. A big disadvantage of SOI circuits is the presence of floating body effects which can be eliminated by careful design and fabrication. C C - + The first topology shown in Figure 5 is an application specific op-amp. It has been designed specifically for the development of an op-amp based high voltage bandgap reference circuit depicted in Figure 1 [5], in SOI processes. Simulation results of op-amp based bandgap references show that the gain required of the op-amp need not be very high. A gain as low as 300 V/V is sufficient to give good results for this bandgap reference. The proposed op-amp architecture is based on the standard two-stage op-amp architecture shown in Figure 2 using p-channel input transistors to optimize slew rate, unity-gain frequency and 1/f noise [8]. It is evident from Figure 1 that the DC voltages required at the input of the op- V i n Figure 2. INPUT STAGE SECOND GAIN STAGE General Two-Stage Op-amp OUTPUT BUFFER V o u t
The op-amp uses a beta multiplier self-bias stage which makes the circuit independent of power supply variations and temperature. The beta multiplier biasing scheme is shown in Figure 3 (start-up circuitry not shown). It is an extended version of a low voltage beta multiplier with more number of stacked MOSFETs to drop the supply voltage so that the drain-source voltages of the MOSFETs are well below their breakdown voltages. The beta multiplier stage biases a high voltage stacked MOSFET current mirror as shown in Figure 5 which in turn supplies the bias current to the input transistors of the op-amp. The stacked MOSFET current mirror imposes a restriction on the input common mode range of the op-amp. VDD V D D Vin+ Vin- C C Figure 3 : High voltage Beta Multiplier V OUT V D D GND Figure 5. The first high voltage op-amp topology I Bias Figure 4. stacked MOSFET current mirror with bias The input differential pair of the op-amp can have only one current mirror load because of the constraint on the DC bias voltages at the inputs. The intrinsic gain of a MOSFET in this process has been found from simulations to be only about 400 V/V which necessitates the presence of a second common source gain stage with a high voltage current source load. The op-amp has to be present in a resistive feedback configuration as seen in Figure 1, hence an output source follower stage is necessary. The gain obtained from the differential pair first stage of the op-amp is approximately g m (r op //r on ). The second stage offers a gain of about g m r o since the stacked current source stages as loads present a very high resistance in parallel with the drain resistance of a single MOSFET. The overall gain of the circuit then comes out to be approximately g m 2 r o 2 /2. The op-amp has a low bandwidth because of the current source loads on the second gain stage. The bias current is taken as low as possible to ensure the maximum gain
possible. The CMRR of this circuit is high. The output swing allows a much greater signal swing than that obtainable from is low and both input common mode ranges are low because the first topology. The CMRR for this topology is high of the current source stack employed to bias the input differential pair. The PSRR of this topology is good because because of the high differential gain. The input common mode ranges are low as for the previous topology. The bandwidth is of the self bias stage. Compensation: Lead compensation is employed for stabilizing the op-amp. The zero nulling resistor is not shown in the circuit. VDD OUTPUT V i n + V i n - Cc Figure 6. Gain Vs Frequency plot for Op-amp 1 Simulation results: The simulation results for the op-amp are shown in Figure 6. Figure 6 shows the op-amp gain plotted against frequency. The gain of the op-amp is about 52 db which is sufficient for the design of high voltage bandgap references using op-amps. III. The Second Op-Amp Topology The second topology shown in Figure 7 is a general purpose op-amp. It s architecture is also based on the two-stage opamp shown in Figure 2. It uses a symmetrical beta multiplier biasing stage so that better power supply insensitivity is obtained. The differential pair first stage has cascoded PMOS and NMOS transistor loads to obtain higher gain. A second common source stage is used to further boost the gain. The diode connected MOSFETs that serve as loads for the common source second stage MOSFET drop the high supply voltages so that the MOSFETs drain-source voltages do not exceed their limits. This op-amp has an output stage different from the first topology. The output buffer in this architecture Figure 7. The second op-amp topology GND high because of the diode connected MOSFETs. This op-amp topology is a modification of existing low voltage topologies to enable high voltage operation.
Compensation: Lead compensation, similar to the one in the first topology is employed for stabilizing the op-amp. The zero nulling resistor is not shown in the circuit. Simulation results: The simulation results for the general purpose op-amp show a gain of approximately 78dB as seen in Figure 8. The gain can be increased by using current mirror cascodes instead of diode connected MOSFETs in the second gain stage at the cost of bandwidth. - A general purpose op-amp has been designed by extending the application specific op-amp. Future tasks are the layout and fabrication of the op-amps. It is expected that there will be design challenges in the layout. References [1] J.C. Stiff, High Voltage Analog circuit design in a 5V 0.8µ partially depleted SOI process, (M.S. thesis,school of ECE, University of Idaho, Moscow, Idaho), August 2003. [2] S. Subramaniam, High Voltage Reference Circuit Designs in a Complementary Metal Oxide Semiconductor (CMOS) Partially Depleted Silicon-on- Insulator (PDSOI) 0.35µm Process, (M.S. Thesis, School of ECE, University of Idaho, Moscow, Idaho), October 2001. [3] R.J. Baker, H.W. Li and D.E. Boyce, CMOS circuit design, layout and simulation, IEEE press, 1998. [4] R.J. Baker, CMOS circuit design, layout and simulation, 2 nd edition, IEEE press, 2005. [5] B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2002. [6] V. Sukumar et al, High Voltage bandgap reference design using SOI technology, Proceeding of the University/Government/Industry Microelectronics Symposium, 30 June-2 July 2003. [7] A. Perlinger, S. Subramanian, V. Sukumar, H.W. Li and H.L Hess, Temperature independent high voltage reference design in silicon on insulator CMOS technology, Industrial Electronics Society, 2004. IECON 2004. 30 th Annual Conference of IEEE Volume 3, 2004 Page(s):3231-3234 [8] D.A. Johns and K. Martin, Analog integrated circuit design, John Wiley and sons, 1997 Figure 8. Gain Vs Frequency plot for op-amp 2 IV. Summary and Conclusions Two high voltage op-amp topologies have been presented and their characteristics examined and compared. The simulation results are for supply voltages of 18V. The first opamp topology is application specific and the second one is for more general purpose applications. Chip area is a very important factor when designing stacked MOSFET architectures and hence the MOSFETs have been designed with small lengths at the expense of gain. The results show the feasibility of high-voltage op-amp design in a low-voltage process. - a high voltage op-amp topology for use in a bandgap has been designed by extending low voltage building blocks to high voltage building blocks by using stacked transistors. These building blocks are a beta multiplier, high voltage current mirrors, differential pairs and high voltage common-source and source-follower amplifiers.