Xilinx XC5VLX50 FPGA UMC 65 nm Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2006 Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. SAR-0612-801 10853JMKG Revision 1.0 Published: December 12, 2006 Revision 2.0 Published: April 7, 2010
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Overview 3.1 XC5VLX50 FPGA Package 4 Process Analysis 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Transistors and Poly 4.7 I/O Transistors 4.8 Isolation 4.9 Wells and Substrate 5 8T SRAM Cell Analysis 5.1 Overview 5.2 Plan View Analysis 5.3 Cross-Sectional Analysis (Perpendicular to Wordline) 5.4 Cross-Sectional Analysis (Parallel to Wordline) 6 Materials Analysis 6.1 Overview 6.2 TEM-EDS Analyses of the Dielectrics 6.3 TEM-EDS Transistors, Contacts, and Poly 6.4 TEM EDS and EELS Analyses of the Metallization
Structural Analysis 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package View 2.1.2 Bottom Package View 2.1.3 Package X-Ray Top View 2.1.4 XC5VLX50-FF676AGU0617 Die Photograph 2.1.5 Die Markings 2.1.6 Annotated Poly Die Photograph 2.1.7 Die Cross Sections 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Bond Pads 2.2.6 NOR Gate 2.2.7 Long Gate Length Transistors 3 Package Overview 3.1.1 Package with Lid Removed 3.1.2 Printed Wiring Board 3.1.3 Die Edge and Underfill 3.1.4 Die and Solder Bumps 3.1.5 Bump Pad 3.1.6 Package Solder Ball 3.1.7 Minimum Pitch PWB Metallization 4 Process Analysis 4.1.1 General View of XC5VLX50 4.1.2 Die Edge 4.1.3 Die Seal 4.2.1 Bond Pad 4.2.2 Left Bond Pad Edge 4.3.1 Passivation 4.3.2 Upper Interlevel Dielectrics 4.3.3 TEM ILD 9 4.3.4 Intermediate Interlevel Dielectrics 4.3.5 TEM ILD 8 and ILD 7 4.3.6 ILD 5 and ILD 4 4.3.7 TEM ILD 4 4.3.8 ILD 3 to ILD 1 4.3.9 TEM ILD 3 and ILD 2 4.3.10 PMD 4.3.11 TEM PMD 4.4.1 Minimum Pitch Metal 12
Overview 1-2 4.4.2 Metal 12 Bottom Barrier Layers 4.4.3 Minimum Pitch Metal 11 4.4.4 Minimum Pitch Metal 10 4.4.5 Minimum Pitch Metal 9 4.4.6 Minimum Pitch Metal 8 and Metal 7 4.4.7 Minimum Pitch Metal 6 4.4.8 TEM Minimum Pitch Metal 5 4.4.9 TEM Minimum Pitch Metal 4 4.4.10 TEM Minimum Pitch Metal 3 4.4.11 TEM Minimum Pitch Metal 2 4.4.12 Minimum Pitch Metal 1 4.5.1 TEM Edge of Via 11 4.5.2 Minimum Pitch Via 10s 4.5.3 Minimum Pitch Via 9s 4.5.4 Minimum Pitch Via 8s 4.5.5 Minimum Pitch Via 7s 4.5.6 Minimum Pitch Via 6s 4.5.7 TEM Minimum Pitch Via 5s 4.5.8 TEM Minimum Pitch Via 4s and 3s 4.5.9 TEM Minimum Pitch Via 2s 4.5.10 TEM Minimum Pitch Via 1s 4.5.11 Minimum Pitch Contacts to Diffusion 4.5.12 TEM Contacts to Diffusion 4.5.13 TEM Contact Top 4.5.14 TEM Contact Bottom 4.5.15 Contacts to Poly 4.6.1 NMOS Transistors 4.6.2 PMOS Transistors 4.6.3 TEM PMOS Transistor 4.6.4 TEM NMOS Transistor 4.6.5 TEM SRAM Gate Oxide 4.6.6 TEM Long Gate Length Transistor 4.6.7 TEM Long Transistor Gate Oxide 4.6.8 EELS Long Transistor Gate Oxide 4.7.1 TEM I/O Transistor and Source/Drain Contacts 4.7.2 TEM I/O Transistor 4.7.3 I/O Transistor Sidewall Spacer 4.7.4 TEM I/O Transistor Gate Oxide 4.8.1 Poly Over Isolation 4.8.2 Minimum Width STI 4.9.1 TEM Diffraction Pattern 4.9.2 SCM N-Well and P-Well 4.9.3 SRP P-Well
Overview 1-3 5 8T SRAM Cell Analysis 5.1.1 8T Dual-Port SRAM 5.2.1 Metal 3 Wordlines and V DD Buses 5.2.2 Metal 2 Bitlines and V DD Buses 5.2.3 Metal 1 Cross-Connects 5.2.4 SRAM at Poly 5.2.5 SRAM at Diffusion 5.3.1 SRAM Perpendicular to Wordline 5.3.2 NMOS Access and Pull-Down Transistors 5.3.3 PMOS Pull-Up Transistors 5.4.1 NMOS and PMOS Gate Widths 5.4.2 NMOS Access Transistor Gate Widths 6 Materials Analysis 6.2.1 TEM-EDS Passivation 6.2.2 TEM-EDS ILD 11 6.2.3 TEM-EDS ILD 9 6.2.4 TEM-EDS ILD 7 6.2.5 TEM-EDS ILD 5 6.2.6 TEM-EDS ILD 4 6.2.7 TEM-EDS ILD 3 6.2.8 TEM-EDS ILD 2 6.2.9 TEM-EDS ILD 1 6.2.10 TEM-EDS 6 Through PMD 3 Layers 6.2.11 TEM-EDS PMD 2 and PMD 1 Silicon Nitride Layers 6.3.1 NMOS Gate Silicide 6.3.2 NMOS Source/Drain Silicide 6.3.3 TEM-EDS Sidewall Spacer 6.4.1 TEM-EDS Metal 12 TiN Barrier 6.4.2 TEM-EDS Metal 12 Ta Barrier 6.4.3 EELS Metal 11 Liner 6.4.4 EELS Metal 1 Liner
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package, Die and Bond Pad Sizes 4 Process Analysis 4.3.1 Dielectric Thicknesses 4.4.1 Metallization Vertical Dimensions 4.4.2 Metallization Horizontal Dimensions 4.5.1 Via and Contact Dimensions 4.6.1 Transistor Horizontal Dimensions 4.6.2 Transistor and Polycide Vertical Dimensions 4.9.1 Die Thickness and Well Depths 5 8T SRAM Cell Analysis 5.2.1 SRAM Dimensions 7 Critical Dimensions 7.1.1 Package, Die and Bond Pads 7.1.2 Minimum Pitch Metals 7.1.3 Minimum Pitch Contacts and Vias 7.1.4 Peripheral Transistor Horizontal Dimensions 7.1.5 SRAM Cell Dimensions 7.2.1 Vertical Dimensions Dielectrics 7.2.2 Vertical Dimensions Metals 7.2.3 Transistor Vertical Dimensions 7.2.4 Die and Wells Vertical Dimensions