A 9.35-ENOB, 14.8 fj/conv.-step Fully- Passive Noise-Shaping SAR ADC Zhijie Chen, Masaya Miyahara, Akira Matsuzawa Tokyo Institute of Technology Symposia on VLSI Technology and Circuits
Outline Background and motivation Conventional Noise shaping technique Proposed fully passive noise shaping SAR ADC Experimental results Conclusion Slide 1
Background and Motivation SAR ADC architecture: VREFP VCM VREFN Switch and Capacitor Comparator Digital V in 4C 2C CLK C C D Q Clk Q Sample Conversion SAR logic SAR ADC mainly consists of digital circuits It can benefit from the technology scaling (like speed) Analog components affect the performance Slide 2
Switch and Capacitor in SAR ADC Capacitor array affects SAR ADC performance VREFP VCM VREFN Switch and Capacitor V in 4C 2C CLK C C D Q Clk Q Sample Conversion SAR logic Higher resolution Larger cap Larger settling time Larger cap Larger chip size Slower speed Slide 3
VREFP VCM VREFN VREFP error Non-ideal effects VREFN Settling error Mismatch V in 3.9C 2.1C CLK jitter C Jitter V N C noise D Q Clk Non-ideal effects further degrade performance How to improve the resolution? Q SAR logic Slide 4
Noise shaping technique Move noise out of band of interest X - Integrator DAC Quantizer Y -100 OSR -150 10 4 10 5 10 6 10 7 10 8 Sacrifice speed for resolution Noise shaping is based on integrator, usually opamp PSD [db] 0-50 PSD of Sigma-Delta Modulator Bandwidth Noise Shaping Order Frequency [Hz] Slide 5
Simulation results of non-ideal effects ENOB (Bits) ENOB (Bits) 10.5 10 9.5 9 8.5 8 SAR 7.5 NS SAR 0.01 0.05 0.1 0.15 0.2 0.25 Comparator noise: Vn (σ(lsb)) 10.5 10 9.5 9 8.5 ENOB (Bits) ENOB (Bits) 10.5 Noise shaping reduces non-ideal effects 10 9.5 9 8.5 8 SAR 7.5 NS SAR 0.1 0.5 1 1.5 2 Settling error (LSB) 10.5 Fin = 6.24 MHz 8 SAR 8 SAR 7.5 NS SAR 7.5 NS SAR 0.1 0.5 1 1.5 2 10 40 70 100 DAC mismatch (LSB) Jitter (ps) 10 9.5 9 8.5 Slide 6
Noise shaping effect on capacitance Traditional SAR ADC Thermal noise = kt/c Noise shaping SAR ADC Thermal noise = (1-Z -1 ) kt/c/osr Same SNR, smaller capacitor for noise shaping SAR ADC Slide 7
Outline Conventional Noise shaping technique Slide 8
Conventional noise shaping technique FIR Filter D out (z) V IN (z) Cap Array Opamp Q(z) V IN (z) a 1 z -1 k A D out (z) a 2 z -1 z -1 FIR Filter IIR Filter FIR filter introduces extra noise and extra area; Opamp : extra power and flicker noise Tech. scaling, difficult to design high performance Opamp [1] J. Fredenburg, et al., JSSC 2012 Slide 9
Outline Proposed fully passive noise shaping SAR ADC Slide 10
Traditional architecture Traditional 1st-order noise shaping architecture SAR ADC X OTA based integrator E Z -1 Y 1-Z -1 - X SAR,in E: quantization noise Y=X+(1-Z -1 )E Y=(X-Z -1 E)+E DAC Previous residue Y(N)=X(N)+X SAR,in (N-1)-Y(N-1)+E(N) Slide 11
Proposed FPNS-SAR ADC architecture Proposed noise shaping architecture (FPNS-SAR) : Realized by Charge redistribution E X in X SAR,in =X in - Z -1 E Y SAR Z -1 -E DAC Step 1: Get previous residue on top-plate of C-DAC; Step 2: Feed it back to input. Slide 12
Residue in SAR ADC Residue on the top-plate of SAR ADC CLK N-1 N VREFP VCM VREFN V in 4C CLK 2C C V top C D Q Clk Q SAR logic After conversion @ N-1, residue V top (N-1)=X SAR,in (N-1)-Y(N-1) Slide 13
FPNS-SAR ADC implementation 1. Conversion @ N-1 2. Clear Charge@ Φ NS2 N-1 N N-1 N Ф S Ф C Ф NS1 Ф NS2 Ф NS3 Ф S C 1 C 2 V in Ф C Ф NS1 Ф NS3 V top + Ф S - Ф S Ф C Ф NS1 Ф NS2 Ф NS3 V in C 1 C 2 Ф C Ф NS1 Ф NS3 V top + - C 3 Ф NS2 C 3 Ф NS2 After conversion, V top =-E(n-1)/2; Clear Charge of C 3, Q C3 =0; Slide 14
FPNS-SAR ADC implementation 3. Charge share @ Φ NS3 4. Sample @ N N-1 N N-1 N Ф S Ф C Ф NS1 Ф NS2 Ф NS3 Ф S C 1 C 2 V in Ф C Ф NS1 Ф NS3 V top + Ф S - Ф S Ф C Ф NS1 Ф NS2 Ф NS3 V in C 1 C 2 Ф C Ф NS1 Ф NS3 V top + - C 3 Ф NS2 C 3 Ф NS2 Get half top voltage, V C3 = V top (n-1)/2; Sampling input, V in (n); Slide 15
5. Conversion@ N FPNS-SAR ADC implementation N-1 N With the help of C 2 and C 3 : Ф S Ф C Ф NS1 Ф NS2 Ф NS3 Ф S C 1 C 2 V in Ф C Ф NS1 Ф NS3 C 3 V top + - Ф NS2 V DAC (n) = V in (n)-e(n-1)+e(n) V DAC (Z) = V in (Z)+(1-Z -1 )E(Z) Realize 1st-order NS Slide 16
Traditional 10b SAR-ADC V in Ф S Ф C C: 8b C-DAC Capacitance comparison C C 2C Proposed 10b noise shaping architecture (FPNS-SAR) + - Total: 4 X C Ф S C 1 C 2 Ф C C 1 =C 2 =C 3 Ф NS1 Ф NS3 C 3 + - Ф NS2 Total: 3 X C 1 C 1 <C, hence, proposal saves area Slide 17
V in Ф S Circuit details Total Circuit of FPNS-SAR ADC: 8-bit Ф NS1 C 1 C 2 + + - V top Ф NS3 C 3 Ф NS2 Ф C SAR Logic Ф S :Bootstrap switch Ф NS2 :NMOS Switch Ф NS1 :CMOS Switch Ф NS3 :NMOS Switch Asynchronous logic; 8-bit C-DAC Different switches; four inputs comparator Slide 18
Circuit details Dynamic comparator [4] CLK AVDD cn cn SR LATCH: Vp cp V inp V inp,p V inn,n V inn cp Vn CLK Dynamic comparator, save power [4] H. Wei, et al., JSSC 2012 Slide 19
Outline Experimental results Slide 20
53.4 µm Chip photograph 230.1 µm CMOS 65 nm CLK LOGIC COMP C-DAC Slide 21
PSD [db] Experimental results Realized 1st-order Noise Shaping 0-20 -40-60 -80-100 -120-140 Power Spectral Density SNDR = 58.03 db ENOB = 9.35 bits Fin = 999.5 khz OSR = 4 Fs = 50 MHz BW = 6.25 MHz 20dB/Oct 10 4 10 5 10 6 10 7 Frequency [Hz] SNDR [db] Power supply: 0.8-V Power : 120.7-µW 60 50 40 30 20 10 0-60 -50-40 -30-20 -10 0 input signal [dbfs] Slide 22
Experimental results-comparison JSSC 10 [2] JSSC 12 [3] JSSC 12 [1] This work Architecture SAR CT-SDM NS-SAR FPNS-SAR Noise Shaping OTA No No Yes Yes Yes Yes Yes No Technology (nm) 65 130 65 65 Bandwidth (MHz) 0.5 15.6 11 6.25 Core Area (mm 2 ) 0.0259 0.27 0.0323 0.0123 Supply (V) 1 1.3 1.2 0.8 Power (μw) 1.9 4000 806 120.7 ENOB (bits) 8.75 9.6 10 9.35 FoM W (fj/conv.) 4.42 160 35.8 14.8 [1] J. A. Fredenburg, et al., JSSC 2012 [2] M. V. Elzakker, et al., JSSC 2010 [3] A. Jain, et al., JSSC 2012 Slide 23
Outline Conclusion Slide 24
Conclusion First work that realizes Passive noise shaping SAR, save power; Maintain basic architecture and operation of SAR- ADC, inherits advantage of SAR-ADC; No Opamp, most are digital circuits, robust to future technology and power supply downscaling; Relax the requirement of circuit blocks, save area and save power. Slide 25
Acknowledgements This work was partially supported by HUAWEI, Mentor Graphics for the use of the Analog Fast SPICE (AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc. Slide 26