EE241 - Spring 2010 Advanced Digital Integrated Circuits TuTh 3:30-5pm 293 Cory Practical Information Instructor: Borivoje Nikolić 550B Cory Hall, 3-9297, bora@eecs Office hours: M 10:30am-12pm Reader: TBA tba@eecs Admin: Rosita Alvarez-Croft 253 Cory Hall, 3-4976, rosita@eecs Class Web page http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s10 2 1
Class Topics This course aims to convey a knowledge of advanced concepts of circuit design for digital VLSI components in state-of-the-art the art MOS technologies. Emphasis is on the circuit design, and optimization for both high performance high speed and low power for use in applications such as microprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, variability, power distribution ib ti and consumption, and timing. 3 EECS141 vs. EECS241 EECS 141: Basic transistor and circuit models Basic circuit design styles First experiences with design creating a solution given a set of specifications EECS 241: Transistor models of varying accuracy Design under constraints: power-constrained, flexible, robust, Learning more advanced techniques Study the challenges facing design in the coming years Creating new solutions to challenging design problems 4 2
EECS141 vs. EECS241 EECS141 0.25 m and 90nm CMOS Unified transistor model Basic circuit design techniques Well defined design project Cadence/Hspice Focus on principles EECS241 Mostly 45nm CMOS Different models Advanced circuit techniques Open design/research project Any tool that does the job Focus on principles 5 Special Focus in Spring 2010 Current technology issues Process variations Robust design SRAM Power and performance optimization Timing 6 3
Class Topics Fundamentals - Technology and modeling Scaling and its limits (2 weeks) Introduction to variability: SRAM example (3 weeks) Sources of variability, modeling SRAM in scaled technologies Timing and variability-aware design (1 week) Power-performance tradeoffs in design (1 week) High-performance design (3 weeks) Domino logic Adders, multipliers Low power design (3 weeks) Timing (1 week) Timing analysis, flip-flop/latch design, clock skew, clocking strategies, selftimed design, clock generation and distribution, phase-locked loops Project presentations (1 week) 7 Class Organization 4 (+/-) assignments (20%) 4 quizzes (10%) 1 term-long design project (40%) Phase 1: Proposal (week of ISSCC) Phase 2: Study (report by week 8) Phase 3: Design (presentation and report by final week) Report and presentations, May 4 Final exam (30%) (Thursday, April 29, in-class) 8 4
Class Material Text: J. Rabaey, Low Power Design Essentials, Springer 2009. Available at www.springerlink.com Baseline: Digital Integrated Circuits - A Design Perspective, 2 nd ed. by J. M. Rabaey, A. Chandrakasan, B. Nikolić Other reference books: Design of High-Performance Microprocessor Circuits, edited by A. Chandrakasan, W. Bowhill, F. Fox Low-Power Electronics Design, C. Piguet, Ed. CMOS VLSI Design, 3 rd ed, N.Weste, D. Harris High-Speed CMOS Design Styles, by K. Bernstein, et al. Leakage in Nanometer CMOS Technologies, by Narendra and Chandrakasan, Ed. Digital Systems Engineering by W. Dally 9 Class Material List of background material available on web-site Selected papers will be made available on web-site Linked from IEEE Xplore and other resources Need to be on campus to access, or use library proxy, library VPN (check http://library.berkeley.edu) Class-notes on web-site No printed handouts in class! 10 5
Sources IEEE Journal of Solid-State Circuits (JSSC) IEEE International Solid-State Circuits Conference (ISSCC) Symposium on VLSI Circuits (VLSI) Other conferences and journals 11 Project Topics Focus this semester: Resiliency Can span from architecture to technology Immunity to variations and soft errors in logic and SRAM Variability compensation Delay monitoring Adaptive designs Power-performance tradeoffs Temperature, supply, noise measurements Or a topic of interest to you 12 6
Tools HSPICE You need an instructional account Predictive sub-100nm models (former BPTM) http://www.eas.asu.edu/~ptm/ 0.18 /0.13/0.09 m CMOS device models on the class web site Other tools, schematic or layout editors are optional Cadence, Synopsys, available on instructional servers More information on the web site. 13 EE241 - Spring 2010 Advanced Digital Integrated Circuits Lecture 1: Introduction Trends and Challenges in Digital Integrated Circuit Design 7
Suggested Reading International Technology Roadmap (http://public.itrs.net) Rabaey, LPDE, Ch 1 (Introduction) Baseline: Rabaey et al, DIC Chapter 3. Chandrakasan, Bowhill, Fox, Chapter 1 Impact of physical technology on architecture (J.H. Edmondson), Chandrakasan, Bowhill, Fox, Chapter 2 CMOS scaling and issues in sub-0.25 m systems (Y. Taur) Selected papers from the web: G.E. Moore, No exponential is forever: but "Forever" can be delayed! Proc. ISSCC 03, Feb 2003. T.-C. Chen, Where CMOS is going: trendy hype vs. real technology. Proc. ISSCC 06 06, Feb 2006. S. Chou, Innovation and Integration in the Nanoelectronics Era, Proc. ISSCC 05, Feb. 2005. S. Borkar, Design challenges of technology scaling, IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999. The contributions to this lecture by a number of people (J. Rabaey, S. Borkar, etc) are greatly appreciated. 15 Semiconductor Industry Revenues M. Chang, Foundry Future: Challenges in the 21 st Century, ISSCC 2007 16 8
Moore s Law In 1965, Gordon Moore noted that the number of transistors t on a chip doubled d every 12 months. He made a prediction that semiconductor technology will double its effectiveness every 12 months 18 24 The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. Gordon Moore, Cramming more Components onto Integrated Circuits, (1965). 17 Transistors Per Die 10 10 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 10 0 Moore s Law - 1965 Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. Electronics, Volume 38, Number 8, April 19, 1965 1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 Graph from S.Chou, ISSCC 2005 1965 Data (Moore) Source: Intel 18 9
Transistors Per Die 10 10 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 10 0 Moore s Law - 2005 1K 512M 1G 2G 256M 128M Itanium 2 Processor 64M 16M Itanium Processor 4M Pentium 4 Processor 1M Pentium III Processor 256K Pentium II Processor Pentium Processor 64K 16K 486 Processor 4K 386 Processor 8080 80286 8086 8008 4004 1965 Data (Moore) Memory Microprocessor 1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 Graph from S.Chou, ISSCC 2005 Source: Intel 19 Moore s law and cost 20 10
Progress in Nano-Technology Millipede Spintronic device Spintronic Storage Molecular Electronics Silicon Nanowires Nanomechanics T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC 06 Carbon Nanotubes 21 Technology Strategy / Roadmap 2000 2005 2010 2015 2020 2025 2030 Plan A: Extending Si CMOS R D Plan B: Subsytem Integration R D Plan C: Post Si CMOS Options R R&D Plan Q: Quantum Computing R T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC 06 D 22 11
Technology Evolution International Technology Roadmap for Semiconductors - 2003 data Year 2004 2007 2010 2013 2016 Dram ½ pitch [nm] 90 65 45 32 22 MPU transistors/chip 550M 1100M 2200M 4400M 8800M Wiring levels 10-14 11-15 12-16 12-16 14-18 High-perf. physical gate [nm] 37 25 18 13 9 High-perf. V DD [V] 1.2 1.1 1.0 0.9 0.8 Local clock [GHz] 4.2 9.3 15 23 40 High-perf. power [W] 160 190 220 250 288 Cost-perf. power [W] 84 104 120 138 158 Low-power V DD [V] 0.9 0.8 0.7 0.6 0.5 Low-power power [W] 2.2 2.5 2.8 3.0 3.0 23 Acceleration in the Past Decade 24 12
ITRS 08 Projections 25 Printed vs. Physical Gate 10 Nominal feature size 10000 m 1 0.1 Gate Length 250nm 180nm 0.7X every 2 years 130nm 90nm 65nm 45nm 32nm 70nm 22nm 50nm 35nm ~30nm 1000 nm 100 0.01 1970 1980 1990 2000 2010 10 2020 2010 2020 Physical gate length > nominal feature size after 22nm? Source: Intel, IEDM presentations 26 13
Some Recent Devices In production: 45nm high-k strained Si In research: 10nm device L = 10 nm g K. Mistry, IEDM 07 Corresponds to sub-22nm node (~10 years) 27 Some Recent Devices Intel s 30nm transistor, circa 2002 Ion = 570 m/ m Ioff = 60nA/ m [B. Doyle, Intel] 28 14
More Recent Devices Intel s 20nm transistor, circa 2002 @0.75V [B. Doyle, Intel] 29 More Recent Devices Thin-Body SOI MOSFET SOI: Silicon-on-Insulator Cheng, IEDM 09 30 15
Sub-5nm FinFET Gate Silicon Fin Source BOX Gate Drain Si fin - Body! X. Huang, et al, IEDM 1999. Lee, VLSI Technology, 2006 31 Major Roadblocks 1. Managing complexity How to design a 10 billion transistor chip? And what to use all these transistors for? 2. Cost of integrated circuits is increasing It takes >$10M to design a chip Mask costs are more than $3M in 45nm technology 3. The end of frequency scaling - Power as a limiting factor Dealing with leakages 4. Robustness issues Variations, SRAM, soft errors, coupling 5. The interconnect problem 32 16
Next Lecture Impact of technology scaling Characteristics of sub-100nm technologies 33 17