Texas Instruments BRF6350B UMC 90 nm RF CMOS Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Inductors 3.8 Isolation 3.9 Wells and Substrate 4 Memory Cell Analyses 4.1 Overview 4.2 Plan-View Analysis High Density 6T SRAM 4.3 Cross-Sectional Analysis (Perpendicular to Wordline) 5 Critical Dimensions 5.1 Package and Die 5.2 Vertical Dimensions 5.3 Vertical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package X-Ray Top View 2.2.1 Die Photograph 2.2.2 Die Markings 2.2.3 Annotated Die Photograph Analysis Sites 2.3.1 Die Corner a 2.3.2 Die Corner b 2.3.3 Die Corner c 2.3.4 Die Corner d 2.3.5 Minimum Pitch Bond Pads 3 Process 3.1.1 General Structure 3.1.2 Die Edge Seal 3.1.3 Die Thickness 3.2.1 Ball Bond to Bond Pad 3.3.1 Passivation and ILD 5 3.3.2 Passivation 3.3.3 ILD 4 through ILD 1 3.3.4 ILD 4 and ILD 3 3.3.5 ILD 2 TEM 3.3.6 ILD 1 TEM 3.3.7 Pre-Metal Dielectric 3.3.8 PMD TEM 3.4.1 Minimum Pitch Metal 6 3.4.2 Metal 6 Cap Layer TEM 3.4.3 Metal 6 Barrier Layers TEM 3.4.4 Minimum Pitch Metal 5 3.4.5 Minimum Pitch Metal 4 3.4.6 Minimum Pitch Metal 3 and Metal 2 3.4.7 Metal 3 TEM 3.4.8 Minimum Pitch Metal 1 in Periphery 3.5.1 Minimum Pitch Via 4s 3.5.2 Via 4s TEM 3.5.3 Minimum Pitch Via 3s TEM 3.5.4 Minimum Pitch Via 2s and Via 1s 3.5.5 Minimum Pitch Contacts to Diffusion 3.5.6 Contact to Diffusion TEM
Overview 1-2 3.6.1 NMOS Transistors 3.6.2 PMOS Transistors 3.6.3 NMOS Transistor TEM 3.6.4 PMOS Transistor and Contact TEM 3.6.5 PMOS Transistor TEM 3.7.1 Inductor Structure 1 3.7.2 Inductor Structure 2 3.7.3 Inductor Structure 3 3.7.4 Inductor Structure 3 Cross Section 3.8.1 Minimum Pitch STI 3.9.1 Wells SCM 3.9.2 SRP of P-Well 3.9.3 SRP of Embedded N-Well 4 Memory Cell Analyses 4.1.1 6T SRAM 4.2.1 Metal 3 Bitlines and Power Buses 4.2.2 Metal 2 Wordlines 4.2.3 Metal 1 Local Interconnects 4.2.4 SRAM at Poly 4.2.5 SRAM at Diffusion 4.3.1 Butted Contact TEM
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Package Markings 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.3.1 Die Dimensions 3 Process 3.3.1 Dielectric Thickness 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Peripheral Transistor Horizontal Dimensions 3.6.2 Transistor and Polycide Vertical Dimensions 3.9.1 Die Thickness and Well Depths 4 Memory Cell Analyses 4.2.1 SRAM Dimensions 5 Critical Dimensions 5.1.1 Package and Die Dimensions 5.2.1 Minimum Pitch Metals 5.2.2 Minimum Pitch Contacts and Vias 5.2.3 Peripheral Transistor Horizontal Dimensions 5.2.4 High Density 6T SRAM Cell Dimensions 5.3.1 Vertical Dimensions Dielectrics 5.3.2 Vertical Dimensions Metals 5.3.3 Transistor Vertical Dimensions 5.3.4 Die and Wells Vertical Dimensions
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