November 6, 2006 Samsung K9G8G08U0M-PCB0 Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 High Voltage Transistors 3.8 Fuses 3.9 Isolation 3.10 Wells and Substrate 4 NAND Flash Cell Analysis 4.1 Overview 4.2 Plan View Analysis 4.3 Cross-Sectional Analysis (Parallel to Bitline) 4.4 Cross-Sectional Analysis (Parallel to Wordline) 5 Materials Analysis 5.1 Overview 5.2 TEM-EDS Analyses of the Dielectrics 5.3 TEM-EDS Transistors, Contacts and Poly 5.4 TEM-EDS Metallization
Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 Statement of Measurement Uncertainty 8 References About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package View 2.1.2 Bottom Package View 2.1.3 Package X-Ray (Top View) 2.1.4 K9G8G08U0M-PCB0 Die 2.1.5 Metal 1 Die Photograph 2.1.6 Die Markings 2.1.7 Die Cross Sections 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Die Seal 2.2.6 Bond Pads 2.2.7 Bond Pad 2.2.8 Fuses 2.2.9 Standard Logic 3 Process Analysis 3.1.1 General View of K9G8G08U0M-PCB0 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Bond Pad 3.2.2 Left Bond Pad Edge 3.2.3 Ball Bond 3.3.1 Passivation 3.3.2 IMD 2 3.3.3 IMD 2 and IMD 1 3.3.4 PMD 3.3.5 PMD Flash Array 3.4.1 Minimum Pitch Metal 3 3.4.2 TEM Metal 3 3.4.3 Minimum Pitch Metal 2 3.4.4 TEM Metal 2 3.4.5 Minimum Pitch Metal 1 in Periphery 3.4.6 TEM Minimum Pitch Metal 1 Bitlines 3.4.7 TEM Metal 1 Line 3.4.8 TEM Metal 0 3.4.9 TEM Metal 0 Top 3.5.1 Minimum Pitch Via 2s 3.5.2 Minimum Pitch Peripheral Via 1s 3.5.3 TEM Via 1s 3.5.4 Peripheral Contacts to Diffusion (Glass-Etch)
Overview 1-2 3.5.5 Minimum Pitch Contacts to Diffusion 3.5.6 Bitline Contacts 3.5.7 TEM Contacts Tops 3.5.8 TEM Bitline Contacts Bottoms 3.5.9 Contacts to Poly 3.5.10 Metal 0 Sourceline Contact 3.5.11 Interpoly Via 3.6.1 Minimum Gate Length NMOS Transistor 3.6.2 NMOS Transistors 3.6.3 Minimum Gate Length PMOS Transistor 3.6.4 TEM Peripheral Transistor 3.6.5 TEM Lattice Image Peripheral Gate Oxide 3.6.6 Flash Cell Transistors 3.6.7 TEM Flash Cell Transistors 3.7.1 Row Driver High Voltage Transistor 3.7.2 High Voltage Transistor (Glass Etch) 3.7.3 Drain Extension (Glass Etch) 3.7.4 TEM Gate Edge 3.7.5 TEM High Voltage Transistor (Width Direction) 3.7.6 TEM HV Gate Oxide 3.8.1 Fuse 3.9.1 Poly Over Isolation 3.9.2 Shallow Trench Isolation (STI) 3.9.3 TEM Minimum Width STI 3.10.1 Flash Array Embedded P-Well 3.10.2 SRP Flash Array Embedded P-Well 3.10.3 SRP Peripheral P-Well 3.10.4 SRP Peripheral N-Well 4 NAND Flash Cell Analysis 4.2.1 Metal 3 Control Lines 4.2.2 Metal 2 Control Lines 4.2.3 Metal 1 Bitlines at Array End 4.2.4 Bitlines and Lands 4.2.5 Metal 1 Bitlines 4.2.6 Polycide Wordlines and Select Lines 4.2.7 Floating Gates, Select Gates and Contacts 4.2.8 Floating Gates and Bitline Contacts 4.2.9 Metal 0 Sourceline 4.3.1 Flash Cell Parallel to Bitline 4.3.2 Bitline Contact and Bitline Select Transistors 4.3.3 TEM Bitline Contact and Select Transistors 4.3.4 Common Sourceline Contact and Source Select Transistors 4.3.5 TEM Sourceline Contact 4.3.6 TEM Flash Cell 4.3.7 TEM ONO Interpoly Dielectric
Overview 1-3 4.3.8 TEM Lattice Image of the Gate Oxide 4.3.9 TEM Bitline Select Transistor 4.4.1 Flash Cell (Parallel to Wordline) 4.4.2 Control Gate and Floating Gates 4.4.3 TEM Control and Floating Gates 4.4.4 TEM Floating Gate 4.4.5 TEM Lattice Image ONO Interpoly Dielectric 4.4.6 TEM Tunnel Oxide 4.4.7 TEM Bitline Contacts 5 Materials Analysis 5.2.1 TEM-EDS Passivation 5.2.2 TEM-EDS IMD 2 5.2.3 TEM-EDS IMD 1 5.2.4 TEM-EDS Pre-Metal Dielectric 5.2.5 TEM-EDS STI 5.3.1 TEM-EDS Poly 3 Silicide and Sidewall Spacer 5.3.2 TEMS-EDS Metal 1 W and Poly 3 Tungsten Silicide 5.3.3 TEM-EDS Bitline Contact Silicide 5.3.4 TEM-EDS Bitline Contact Liner 5.4.1 TEM-EDS Metal 2 5.4.2 TEM-EDS Tungsten Metal 1
Overview 1-4 1.2 List of Tables 1 Overview 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package, Die and Bond Pad Sizes 3 Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Peripheral Transistor Horizontal Dimensions 3.6.2 Peripheral Transistor and Polycide Vertical Dimensions 3.10.1 Die Thickness and Well Depths 4 NAND Flash Cell Analysis 4.3.1 Flash Cell Dimensions 6 Critical Dimensions 6.1.1 Package, Die and Bond Pads 6.1.2 Minimum Pitch Metals 6.1.3 Minimum Pitch Contacts and Vias 6.1.4 Peripheral Transistor Horizontal Dimensions 6.1.5 Flash Cell Dimensions 6.2.1 Vertical Dimensions Dielectrics 6.2.2 Vertical Dimensions Metals 6.2.3 Transistor Vertical Dimensions 6.2.4 Die and Wells Vertical Dimensions
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