19-3869; Rev 1; 1/11 Low-oltage, High-Accuracy, Quad Window General Description The are adjustable quad window voltage detectors in a small thin QFN package. These devices are designed to provide a higher level of system reliability by monitoring multiple supply voltages and providing a fault signal when any of the voltages exceed their overvoltage thresholds or fall below their undervoltage thresholds. These devices offer user-adjustable thresholds that allow voltages to be monitored down to 0.4. These devices allow the upper and lower trip thresholds of each window detector to be set externally with the use of three external resistors. Each monitored threshold has an independent opendrain output for signaling a fault condition. The outputs can be wire OR ed together to provide a single fault output. The open-drain outputs are internally pulled up with a 30µA current, but can be externally driven to other voltage levels for interfacing to other logic levels. Both devices feature a margin input to disable the outputs during margin testing or any other time after power-up operations. The offers a reset output that deasserts after a reset timeout period after all voltages are within their threshold specifications. The reset timeout is internally set to 140ms (min), but can be externally adjusted to other reset timeouts using an external capacitor. In addition, the offers a manual reset input. All devices are offered in a 4mm x 4mm TQFN package and are fully specified from -40 C to +125 C. Applications Storage Equipment Networking/Telecommunications Equipment Multivoltage ASICs Servers Features Monitor Four Undervoltage/Overvoltage Conditions 1.5% Accuracy Over Temperature User-Adjustable Thresholds (Down to 0.4) Open-Drain Outputs with Internal Pullups Reduce the Number of External Components Manual Reset Input () Margin Enable Input Fixed or Adjustable Timeout () Guaranteed Correct Output Logic State Down to = 1 Fully Specified from -40 C to +125 C Small, 4mm x 4mm TQFN Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX16008TP+ -40 C to +125 C 20 TQFN TG+ -40 C to +125 C 24 TQFN +Denotes a lead(pb)-free/rohs-compliant package. For tape-and-reel, add a T after the +. Tape-and-reel are offered in 2.5k increments. 3.5 2.5 1.8 1.5 Typical Operating Circuit UIN1 OIN1 UIN2 OIN2 CC UOUT1 OOUT1 UOUT2 OOUT2 μc UIN3 UOUT3 OIN3 OOUT3 UIN4 UOUT4 OIN4 OOUT4 Pin Configurations and Selector Guide appear at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS, OOUT_, UOUT_,, UIN_, OIN_ to...-0.3 to +6 MARGIN, MR, TOL, SRT to...-0.3 to ( + 0.3) Input/Output Current (, MARGIN, SRT, MR, UOUT_, OOUT_)...±20mA Continuous Power Dissipation (T A = +70 C) 20-Pin Thin QFN (derate 16.9mW/ C above +70 C)...1355mW 24-Pin Thin QFN (derate 16.9mW/ C above +70 C)...1666mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Operating Temperature Range...-40 C to +125 C Junction Temperature...+150 C Storage Temperature Range...-65 C to +150 C Lead Temperature (soldering, 10s)...+300 C Soldering Temperature (reflow)...+260 C ( = 2.0 to 5.5, TOL =, T A = -40 C to +125 C, unless otherwise specified. Typical values are at = 3.3, T A = +25 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating oltage Range (Note 2) 1.0 5.5 = 3.3, outputs deasserted 45 65 Supply Current (Note 3) I CC = 5, outputs deasserted 45 70 µa ULO (Undervoltage Lockout) ULO rising 1.62 1.8 1.98 UIN_/OIN_ Adjustable Threshold (UIN_ Falling/OIN_ Rising) TH 0.388 0.394 0.400 UIN_/OIN_ Hysteresis TH _ HYS UIN_ falling/oin_ rising (percentage of the threshold) 0.5 % TH UIN_/OIN_ Input Current I IB -100 +100 na SRT = 140 200 280 Reset Timeout t RP C SRT = 1500pF (Note 4) 2.43 3.09 3.92 C SRT = 100pF 0.206 ms C SRT = open 0.05 SRT Ramp Current I SRT SRT = 0 460 600 740 na SRT Threshold TH_SRT 1.173 1.235 1.293 SRT Hysteresis 100 m UIN_/OIN_ to Reset Delay t RD UIN_ falling/oin_ rising 20 µs 2
ELECTRICAL CHARACTERISTICS (continued) ( = 2.0 to 5.5, TOL =, T A = -40 C to +125 C, unless otherwise specified. Typical values are at = 3.3, T A = +25 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS C C = 3.3, I S IN K = 10m A, RE S E T asser ted 0.30 Output-oltage Low OL = 2.5, I SINK = 6mA, RE S E T asser ted 0.30 = 1.2, I SINK = 50µA, RE S E T asser ted 0.30 Output-oltage High OH 2.0, I SOURCE = 6µA, deasserted MR Input-oltage Low IL 0.3 x 0.7 x MR Input-oltage High IH MR Minimum Pulse Width 1 µs MR Glitch Rejection 100 ns MR to Delay 200 ns MR Pullup Resistance 12 20 28 kω OUTPUTS (UOUT_/OOUT_) UOUT_, OOUT_ Output- oltage Low OOUT_, OOUT_ Output- oltage High U IN _/O IN _ to U O UT_/ O O UT_ Propagation Delay DIGITAL LOGIC Note 1: Devices are tested at T A = +25 C and guaranteed by design for T A = T MIN to T MAX. Note 2: The outputs are guaranteed to be in the correct logic state down to = 1. Note 3: Measured with MR and MARGIN unconnected. Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worse case of the SRT current and SRT threshold specifications. Do not set the reset timeout period to more than 1.12s. Note 5: Amount of time required for logic to lock/unlock outputs from margin testing 0.8 x = 3.3, I SINK = 2mA 0.30 OL = 2.5, I SINK = 1.2mA 0.30 OH 2.0, I SOURCE = 6µA 0.8 x t D ( TH - 100m) to ( TH + 100m) 20 µs TOL Input-oltage Low IL 0.3 x 0.7 x TOL Input-oltage High IH TOL Input Current TOL = 100 na MARGIN Input-oltage Low IL 0.3 x 0.7 x MARGIN Input-oltage High IH MARGIN Pullup Resistance Pulled up to 12 20 28 kω MARGIN Delay Time t MD Rising or falling (Note 5) 50 µs 3
( = 3.3, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (μa) INPUT THRESHOLD 60 55 50 45 40 35 SUPPLY CURRENT vs. SUPPLY OLTAGE MARGIN AND MR UNCONNECTED 30 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY OLTAGE () UIN_/OIN_ THRESHOLD vs. TEMPERATURE 0.45 0.44 0.43 0.42 0.41 0.40 0.39 0.38 0.37 0.36 0.35-40 -25-10 5 20 35 50 65 80 95 110 125 TEMPERATURE ( C) MAX16008 toc01 MAX16008 toc04 SUPPLY CURRENT (μa) OUT_ (m) 65 60 55 50 45 40 35 MARGIN AND MR UNCONNECTED = 5 = 2.5 SUPPLY CURRENT vs. TEMPERATURE 30-40 -25-10 5 20 35 50 65 80 95 110 125 TEMPERATURE ( C) 100 75 50 25 OUTPUT OLTAGE vs. SINK CURRENT Typical Operating Characteristics = 3.3 UOUT_ / OOUT_ LOW 0 0 1 2 3 4 5 6 7 8 SINK CURRENT (ma) MAX16008 toc02 MAX16008 toc05 INPUT THRESHOLD MAXIMUM TRANSIENT DURATION (μs) 0.450 0.425 0.400 0.375 UIN_/OIN_ THRESHOLD vs. SUPPLY OLTAGE 0.350 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY OLTAGE () 600 500 400 300 200 100 MAXIMUM TRANSIENT DURATION vs. INPUT OERDRIE OUTPUT GOES LOW ABOE THIS LINE 0 1 10 100 1000 INPUT OERDRIE (m) MAX16008 toc03 MAX16008 toc06 4
Typical Operating Characteristics (continued) ( = 3.3, T A = +25 C, unless otherwise noted.) TIMEOUT PERIOD (ms) 198 197 196 195 194 193 192 191 TIMEOUT PERIOD vs. TEMPERATURE 190-40 -25-10 5 20 35 50 65 80 95 110 125 TEMPERATURE ( C) UIN_ TO UOUT_ DELAY TIME MAX16008 toc09 MAX16008 toc07 TIMEOUT DELAY 40ms/div MARGIN ENABLE FUNCTION MAX16008 toc08 SRT = MAX16008 toc10 UIN1 1/div UOUT1 2/div 2/div UIN1 2/div MARGIN 2/div UOUT1 2/div UOUT_ 2/div 2/div UIN_ BELOW RESPECTIE THRESHOLDS 4μs/div 100μs/div 5
MAX16008 PIN NAME 1 1 UIN3 2 2 OIN3 3 3 UIN4 FUNCTION Pin Description Undervoltage Threshold Input 3. When the voltage on UIN3 falls below its threshold, UOUT3 Overvoltage Threshold Input 3. When the voltage on OIN3 rises above its threshold, OOUT3 Undervoltage Threshold Input 4. When the voltage on UIN4 falls below its threshold, UOUT4 4 4 OIN4 Overvoltage Threshold Input 4. When the voltage on OIN4 rises above its threshold, OOUT4 5 6 Ground 6, 20 7, 24 Unmonitored Power to the Device 7 8 UOUT3 8 9 OOUT3 9 10 UOUT4 10 11 OOUT4 11 14 MARGIN 12 15 OOUT2 Active-Low Undervoltage Output 3. When the voltage at UIN3 falls below its threshold, UOUT3 asserts low and stays asserted until the voltage at UIN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to. Active-Low Overvoltage Output 3. When the voltage at OIN3 rises above its threshold, OOUT3 asserts low and stays asserted until the voltage at OIN3 falls below its threshold. The open-drain output has a 30µA internal pullup to. Active-Low Undervoltage Output 4. When the voltage at UIN4 falls below its threshold, UOUT4 asserts low and stays asserted until the voltage at UIN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to. Active-Low Overvoltage Output 4. When the voltage at OIN4 rises above its threshold, OOUT4 asserts low and stays asserted until the voltage at OIN4 falls below its threshold. The open-drain output has a 30µA internal pullup to. Active-Low Margin Enable Input. Pull MARGIN low to deassert all outputs (go into high state) regardless of the voltage at any monitored input. Active-Low Overvoltage Output 2. When the voltage at OIN2 rises above its threshold, OOUT2 asserts low and stays asserted until the voltage at OIN2 falls below its threshold. The open-drain output has a 30µA internal pullup to. 6
MAX16008 PIN NAME 13 16 UOUT2 14 17 OOUT1 15 18 UOUT1 16 20 UIN1 17 21 OIN1 18 22 UIN2 FUNCTION Pin Description (continued) Active-Low Undervoltage Output 2. When the voltage at UIN2 falls below its threshold, UOUT2 asserts low and stays asserted until the voltage at UIN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to. Active-Low Overvoltage Output 1. When the voltage at OIN1 rises above its threshold, OOUT1 asserts low and stays asserted until the voltage at OIN1 falls below its threshold. The open-drain output has a 30µA internal pullup to. Active-Low Undervoltage Output 1. When the voltage at UIN1 falls below its threshold, UOUT1 asserts low and stays asserted until the voltage at UIN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to. Undervoltage Threshold Input 1. When the voltage on UIN1 falls below its threshold, UOUT1 Overvoltage Threshold Input 1. When the voltage on OIN1 rises above its threshold, OOUT1 Undervoltage Threshold Input 2. When the voltages on UIN2 falls below its threshold, UOUT2 19 23 OIN2 Overvoltage Threshold Input 2. When the voltage on OIN2 rises above its threshold, OOUT2 5 N.C. Not Internally Connected 12 MR Active-Low Manual Reset Input. Pull MR low to assert low. remains low for the reset timeout period after MR is deasserted. MR is pulled up to through a 20kΩ resistor. 13 SRT 19 EP Set Reset Timeout Input. Connect a capacitor from SRT to to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 10 6 (Ω) x C SRT (F). Do not set the reset timeout period to more than 1.12s. For the internal timeout period of 140ms (min), connect SRT to. Active-Low Reset Output. asserts low when the voltage on any of the UIN_ inputs falls below their respective thresholds, the voltage on any of the OIN_ inputs goes above its respective threshold, or MR is asserted. remains asserted for at least the minimum reset timeout after all monitored UIN_ inputs exceed their respective thresholds, all OIN_ inputs fall below their respective thresholds, and MR is deasserted. This open-drain output has a 30µA internal pullup. Exposed Pad. EP is internally connected to. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PC board. Do not use as the only electrical connection to. 7
UIN1 OIN1 UIN2 (MR) (SRT) TIMING CIRCUIT OUTPUT DRIER () UOUT1 OOUT1 UOUT2 OIN2 OOUT2 UIN3 UOUT3 OOUT3 OIN3 UIN4 UOUT4 OOUT4 OIN4 REFERENCE UNDEROLTAGE LOCKOUT MAX16008/ ( ) ONLY MARGIN Figure 1. Functional Diagram 8
Detailed Description The are adjustable quad window voltage detectors in a small thin QFN package. These devices are designed to provide a higher level of system reliability by monitoring multiple supply voltages and providing a fault signal when any of the voltages exceeds its overvoltage threshold or falls below its undervoltage threshold. These devices offer user-adjustable thresholds that allow voltages to be monitored down to 0.4. The devices allow the upper and lower trip thresholds of each window detector to be set externally with the use of three external resistors. Each monitored threshold has an independent opendrain output for signaling a fault condition. The outputs can be wire OR ed together to provide a single fault output. The open-drain outputs are internally pulled up with a 30µA current, but can be externally driven to other voltage levels for interfacing to other logic levels. Both devices feature a margin input to disable the outputs during margin testing or any other time after power-up operations. The offers a reset output that deasserts after a reset timeout period after all voltages are within their threshold specification. The reset timeout is internally set to 140ms (min), but can be externally adjusted to other reset timeouts using an external capacitor. In addition, the offers a manual reset input. Applications Information oltage Monitoring The feature undervoltage and overvoltage comparators for window detection (see Figure 2). UOUT_/OOUT_ deassert high when the monitored voltage is within the selected window. When the monitored voltage falls below the lower limit of the window ( TRIPLOW ), UOUT_ asserts low; or if the monitored voltage exceeds the upper limit ( TRIPHIGH ), OOUT_ The application in Figure 2 shows the enabling the DC-DC converter when the monitored voltage is in the selected window. +5 R1 R2 R3 UIN_ MAX16008/ OIN_ UOUT_ OOUT_ Figure 2. Monitor Circuit The resistor values R1, R2, and R3 can be calculated as shown: R TRIPLOW TOTAL = TH R2 + R3 R TRIPHIGH = TOTAL TH R3 where R TOTAL = R1 + R2 + R3. Use the following steps to determine the values for R1, R2, and R3: 1) Choose a value for R TOTAL, the sum of R1, R2, and R3. Because the have very low input bias current (2nA typ), R TOTAL can be up to 2MΩ. Large-value resistors help minimize power consumption. Lower-value resistors can be used to maintain overall accuracy. IN EN OUT DC-DC REGULATOR 9
Use the following formulas to calculate the error: R R IIB R + 1 3 1 R + R 2 3 EU (%) = x 100 TRIPLOW I R xr E IB ( + ( )) O (%) = 2 2 1 x 100 TRIPHIGH where E U and E O are the undervoltage and overvoltage error (in %), respectively. 2) Calculate R3 based on R TOTAL and the desired upper trip point: TH xrtotal R3 = TRIPHIGH 3) Calculate R2 based on R TOTAL, R3, and the desired lower trip point: TH xrtotal R2 = R3 TRIPLOW 4) Calculate R1 based on R TOTAL, R3, and R2: R1= RTOTAL R2 R3 Overvoltage Shutdown The are ideal for overvoltageshutdown applications. Figure 3 shows a typical circuit for this application using a pass p-channel MOSFET. The are powered directly from the system voltage supply. Select R1 and R2 to set the trip voltage. When the supply voltage remains below the selected threshold, a low logic level on UOUT_ turns on the p-channel MOSFET. In the case of an overvoltage event, UOUT_ goes high turning off the MOSFET, and shuts down the power to the load. Figure 4 shows a similar application using a fuse and a silicon-controlled rectifier (SCR). An overvoltage event turns on the SCR and shorts the supply to ground. The surge of current through the short circuit blows the fuse and terminates the current to the load. Select R3 so that the gate of the SCR is properly biased when UOUT_ goes high. Unused Inputs Any unused UIN_ inputs must be connected to, and any unused OIN_ inputs must be connected to. UOUT_/OOUT_ Outputs UOUT_ and OOUT_ outputs assert low when UIN_ and OIN_, respectively, drop below or exceed their specified thresholds. The undervoltage/overvoltage outputs are open-drain with a (30µA) internal pullup to. For many applications, no external pullup resistor is required to interface with other logic devices. An external pullup resistor to any voltage up to 5.5 overdrives the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to (Figure 5). When choosing the external pullup resistor, the resistance value should be large enough to ensure that the output can sink the necessary current during a logic-low condition and small enough to be able to overdrive the internal pullup current and meet output high specifications SUPPLY SUPPLY FUSE R1 R2 UIN_ MAX16008/ UOUT_ R3* LOAD R1 R2 UIN_ MAX16008/ UOUT_ R3 SCR LOAD *OPTIONAL. ALUES OF 10kΩ AND ABOE ARE RECOMMENDED. Figure 3. Overvoltage Shutdown Circuit (with External Pass MOSFET) Figure 4. Overvoltage Shutdown Circuit (with SCR Fuse) 10
( OH ). Resistor values of 50kΩ to 200kΩ can generally be used. Output ( Only) asserts low when the voltage on any of the UIN_ inputs falls below its respective threshold, the voltage on any of the OIN_ inputs goes above its respective threshold, or MR is asserted. remains asserted for the reset timeout period after all monitored UIN_ inputs exceed their respective thresholds, all OIN_ inputs fall below their respective thresholds, and MR is deasserted (see Figure 6). This open-drain output has a 30µA internal pullup. Reset Timeout Capacitor The reset timeout period can be adjusted to accommodate a variety of microprocessor (µp) applications from 50µs to 1.12s. Adjust the reset timeout period (t RP ) by connecting a capacitor (C SRT ) between SRT and. Calculate the reset timeout capacitor as follows: t s C F RP () SRT ( ) = TH_ SRT I SRT Do not use capacitor (C SRT ) values higher than 390nF. Connect SRT to for a factory-programmed reset timeout of 140ms (min). Manual Reset Input (MR) ( Only) Many µp-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on MR asserts low. remains asserted while MR is low, and during the reset timeout period (140ms min) after MR returns high. The MR input has an internal 20kΩ pullup resistor to, so it can be left open if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1µF capacitor from MR to provides additional noise immunity. Margin Output Disable (MARGIN) MARGIN allows system-level testing while power supplies are adjusted from their nominal voltages. Drive MARGIN low to deassert all outputs (UOUT_, UIN_ TH_ TH_ + TH_HYS = 3.3 5 90% 100kΩ 10% t RD t RP UOUT_ UOUT_ 10% 90% t D t D MAX16008/ TH_ OIN_ OOUT_ 90% TH_ - TH_HYS 10% Figure 5. Interfacing to a Different Logic Supply oltage Figure 6. Output Timing Diagram t D t D 11
OOUT_, and ) regardless of the voltage at any monitored input. The state of each output does not change while MARGIN =. While MARGIN is low, the IC continues to monitor all voltages. When MARGIN is deasserted, the outputs go to their monitored states after a short propagation delay. The MARGIN input is internally pulled up to. Leave unconnected or connect to if unused. PART NUMBER OF MONITORED LEELS UNDEROLTAGE/ OEROLTAGE THRESHOLDS Power-Supply Bypassing The operate from a 2.0 to 5.5 supply. An undervoltage lockout ensures that the outputs are in the correct states when the ULO is exceeded. In noisy applications, bypass to ground with a 0.1µF capacitor as close to the device as possible. In addition, the additional capacitor improves transient immunity. For fast-rising transients, additional capacitance may be required. ADJUSTABLE TIMEOUT Selector Guide MAX16008 4 Adjustable 4 Adjustable MR Pin Configurations TOP IEW UIN1 OIN1 UIN2 OIN2 UOUT1 15 14 13 12 11 18 17 16 15 14 13 19 12 MR 16 10 OOUT4 UIN1 20 11 OOUT4 17 9 UOUT4 OIN1 21 10 UOUT4 18 8 OOUT3 MAX16008 UIN2 22 9 OOUT3 19 7 UOUT3 OIN2 23 8 UOUT3 20 + 6 + 24 7 1 UIN3 OOUT1 2 OIN3 UIN4 UOUT2 3 OOUT2 OIN4 TQFN 4mm x 4mm MARGIN 4 5 TOP IEW UOUT1 UIN3 OOUT1 1 2 OIN3 UIN4 UOUT2 3 OOUT2 OIN4 TQFN 4mm x 4mm MARGIN N.C. SRT 4 5 6 Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 TQFN-EP T2044+3 21-0139 90-0037 24 TQFN-EP T2444+4 21-0139 90-0022 12
REISION NUMBER REISION DATE DESCRIPTION Revision History PAGES CHANGED 0 10/05 Initial release 1 1/11 Added soldering temperature in the Absolute Maximum Rating section and added symbol in Electrical Characteristics table 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 13 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.