TRUE SYNTHESIZABLE CRITICALPATH AND FALSE PATH FILTERING USING ATPG

TRUE SYNTHESIZABLE CRITICALPATH AND FALSE PATH FILTERING USING ATPG Samarshekar #1, Ramesh S R *2 VLSI Design and Security TAG Department of Electronics and Communication Engineering Amrita School of Engineering, Coimbatore Amrita VishwaVidyapeetham, Amrita University, Coimbatore Tamil Nadu, India 1 samarshekar560@gmail.com 2 sr_ramesh@cb.amrita.edu Abstract Timing analysis is performed to meet the user specified timing constraints of the design. All chips must pass the timing checks and meet user specified the timing constraints of the design before fabrication. Static Timing Analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. The characteristic of Static Timing Analysis (STA) will only consider the delay of each logic gates and cells in the path and does not take the functional behaviour of the logic cells into account.all the timing paths will not activate in real work environment. These paths which are not activated are known as false paths. The traditional Static Timing Analysis (STA) results are overly pessimistic. STA results are estimation as many critical paths are not true paths and most of the critical paths are false paths or non-functional paths. In classic design flow, the critical path delay is calculated through Static Timing Analysis (STA). This approach may leads to erroneous results as STA cannot accurately calculate path delay of all the actual critical paths. This work proves the existence of false paths in ISCAS 85 and ISCAS 89 benchmark circuits by identifying false paths and eliminating them by false path constraints. Elimination of false paths provides area and power advantage. This work aims to generate synthesizable critical path and to reduce the number of false paths by using fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults. Keyword- False paths, Critical paths, STA, DTA, ATPG I. INTRODUCTION Timing analysis is used to perform the timing the constraints of adesign. Timing verification is an important phase in timing analysis as incorrect constraints lead to chip failures [3]. Logic circuits generally consists of large number of paths through which signals cannot propagate in functional mode analysis, these paths known as unsensitizablepaths, or simply false paths [3],[ 4].Traditional timing verificationtechnique such as Static Timing Analysis (STA) is usually too conservative or sometimes too pessimistic [3], [9], 10]. STA main drawback isinability to detect false paths. A false path can also be termed as non-functional paths. Timing analysis tools can report true critical path and false critical paths. The critical paths reported by the timing tools mayor may not be synthesizable. In ASIC design timing analysis can be applied in both pre-layout and post-layout. In pre-layout delay calculation is an estimation of the interconnect delay values. In post-layout timing analysis the delays values are accurate and after floorplanning, placement and routing the standard cells are placed accurately in between the citros of VDD and VSS.STA reported false and true critical path delay values may or may not be true [2]. Moreover static timing analysis cannot provide the details of how many critical paths exists in the circuit.a path can also be called as false path if the transitions on the input cannot be propagated to the output along the path [1].If any one false critical path is right regarded as a critical path, the results are conservative and performance of the circuit would be affected. There may be up to 30% of paths in the circuit that are reported as false paths [3]. So it is predicted that static timing analysis reported critical paths may be false. The corresponding delay of the circuit is may not accurate and overly pessimistic.the main drawbacks of STAis to inability to detect accurate false paths automatically and also the number of false critical paths. The other one is the Static timing analysis is neglect the simultaneous input transitions. The main reason is that static timing analysis is built on single input transitions (SIT) hypothesis [4].The proposed method aims to first identify the false critical paths from true critical paths and optimises the circuit by removing the nonfunctional false critical paths, through dynamic simulation using ATPG filtering. The method also uses falsepath constraints to remove the false paths, without affecting the performance of the circuit. Functionality of each critical path is verified through TetraMAX ATPG. DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2725

II. BACKGROUND A.Static Timing Analysis Static Timing Analysis considers the logic cells delay along the path, these delay values are static such as cell delay, net delay or gate delay. In static timing analysis timing models are built on gate delay and net delays. While propagating along the path max and min values are taken into consideration. Static timing analysis can be applied on pre-layout and post-layout. In pre-layout timing analysis is performed using estimated delay values from standard delay format, and it s an estimation which is not accurate. In post layout timing analysis the extracted parasitic delay values, which are accurate and corresponding critical path delay values will be accurate. B. Dynamic timing analysis The main difference between STA and dynamic timing analysis lies on the fact that STA does not verifies functionality of the design whereas the later verifies the functionality of the design by applying stuck-at faults and pathdelay faults and checking for correct output faults whereas Static Timing Analysis just add the delay in the path without considering the functionality of the design. Dynamic timing analysis utilizes test faults to verify the circuit functionality and computes the accurate timing results for the given set of inputs without any timing violations. Before applying the dynamic timing analysis, the design should not have any violations and the functionality of the design must be cleared. For STA functionality of the design is not important assta only considers the delay of the circuit along the path. Dynamic timing analysis is much more accurate with large number of input vectors. Static timing analysis cannot be applied to asynchronous designs whereas dynamic timing analysis can be applied to asynchronous designs. C. Advantages of STA i. STA considers all the timing paths, whether it may be a functional or non-functional paths [11]. ii. STA analysis time is very fast and exhaustive compared to Statistical static timing analysis (SSTA) and Dynamic timing analysis (DTA) [11]. iii. STA is analysed for best, worst and typical cases, while dynamic simulation it is not possible. iv. Static timing analysis calculates the delay through delay models, STA results are pessimistic in nature and fast. DTA is slow and accurate, as it checks the functionality of the design. DTA is very complex compared to STA. D. Disadvantages of STA i. Since STA is pessimistic and considers the false critical path as false critical path is non-functional path. In general STA critical paths are false in nature. ii. If a false path is considered for circuit delay calculation, the output will be conservative and results are affected. iii. STA will add the delay of the gates and logic cells along the path, it does not take functionality of the design into account. iv. STA cannot be applicable to asynchronous circuits. Advantages of dynamic timing analysis i. Very accurate but slow and the quality depends on input vectors. ii. Dynamic timing analysis is non-exhaustive. E. STA in ASIC design pre-layout Fig.1. STA pre-layout ASIC design flow DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2726

In ASIC design flow static timing analysis is applied in both pre-layout and post-layout. In fig 1 ASIC design flow of pre-layout is shown. In the synthesis phase all the timing requirements clock, input load, output load and user defined timing constraints are specified. Timing analysis is applied to match the user specified design constraints. In design for testing phase design check rule (DRC) is performed to identify all the timing violations, and before floorplanning phase all the timing violations are removed. After floorplanningparasitics are extracted which contains the delay values. F.STA ASIC design flow-post-layout Fig.2. STA post-layout ASIC design flow In post-layout ASIC design flow, in the floorplanning phase timing constraints are specified according to user. All the timing violations are corrected after place and route standard cells are placed accurately on the given die area.from the location of these standard cells parasitics are extracted with accurate interconnect delays. G.False paths Pathcriticality: Critical path can also be called as a path which violates the timing constraints of the design. Criticality of a path is the probability of manufacturing a chip in which the path of interest is critical [5], [9], [10]. Critical path: Critical path is the maximum path in the circuit which violates the timing constraints. False path: STAconsiders the delay of the each gates and logic cell in the propagating path and does not consider behaviour or functionality of the design [8]. All paths will not get a chance to activate in the real circuit. These inactivated paths are referred as false paths. If any of the falsepath is considered as a working critical path, results would be conservative and the performance of the circuit is degraded. Basically false paths occur due to two reasons [3] 1. Functional configuration 2. Path redundancy H.Functional configuration As shown below two input paths of the multiplexers are controlled by the select lines. STA will select the maximum path in the circuit as in3 - B1- M1/B M2/B out (0.2 ns + 0.3 ns + 0.3 ns) = 0.8ns. The path with delay 0.8ns is non-functional path As a result of this some functional paths are not taken into account for timing analysis. In the circuit the path, from in3--b1-- M1/B-- M2/B out never has a chance the opportunity to get activated, but it is the critical path according to STA because of the longest path delay in the circuit [4]. Fig.3. False path led by functional configuration [4] DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2727

I.Path redundancy Due to multiplexers with multiple select lines some paths are activated very rarely. Some select lines are overlapped and never be activated in real circuit. Slower path will be overlapped by the faster paths. The Overlapped paths even which passes throughfunctional paths. If one path is bypassed under all input patterns, it is also a false path. P1: reg_a =>and_a =>and_b =>reg_c 0.2ns P2: reg_b =>and_a =>and_b =>reg_c 0.2ns P3: reg_a => mux =>and_b =>reg_c 0.2ns P4: reg_b => mux =>and_b =>reg_c 0.2ns P5: reg_b =>inv => mux =>and_b =>reg_c 0.4ns Consider all five in the circuit. According to STA p5 is the longest path, but it is actually bypassed and never gets the chance to activate. Fig.4. False path led by redundancy [4] TABLE1.Truth table [4] Reg_a Reg_b Path Reg_c 0 0 P1 0 0 1 P1 0 1 0 P2 0 1 1 P4 1 Fig.5. Input NAND gate cell DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2728

In the figure 5 when A = 0 output is Y from VDD to Y through A.When A = 0 B is always bypassed and B will never have the chance to activated. Hence path B to Y is a false path as it will never get chance to activate in the real work environment. III. OPTIMISATION METHODOLOGY Fig.6. Methodology flow As STA cannot resolve the false path problem, dynamic timing analysis is the solution to the false path problem. The dynamic timing simulation needs a lot of time and effort.as in this methodology optimised gate-level netlist is generated from Design compiler [13]. The gate level netlist is imported to Design of testing (DFT) compiler [16], where scan chain is inserted. Scan-chain inserted netlist is extracted for further requirements. DFT [16] netlist is inserted to ICC compiler [12] where cells are placed and routed correctly. From ICC compiler [12] physical design cell (DB) and post placement netlist are extracted.physical design cell is imported to StarRC [17] to extract RCparasitics. These extracted parasitics and post placement netlist are sent to PrimeTime for timing analysis and critical path extraction. These extracted critical paths are converted to TetraMAX [15] readable critical paths. In TetraMAX [15] stuckat fault are added to all the critical paths to check the functionality of each path. If any path is found to be nonfunctional, it is detected and set as a false path constraint in the PrimeTime. This process of detecting false path and elimination of false path is done until all false paths are eliminated from the circuit. As STA cannot resolve the false path problem, dynamic timing analysis is the solution to the false path problem [7]. The dynamic timing simulation needs a lot of time and effort. Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations [2]. The problem is that the simulation vectors cannot guarantee 100% coverage. The goal for the dynamic analysis is to get a 100% test fault coverage, so that all the paths in the circuit detected.as in this methodology optimised gate-level netlist is generated from Design compiler [13]. The gate level netlist is imported to Design of testing (DFT) compiler [16], where scan chain is inserted. Scan-chain DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2729

inserted netlist is extracted for further requirements. DFT netlist is inserted to ICC compiler [12] where cells are placed and routed correctly. From ICC compiler [12] physical design cell (DB) and post placement netlist are extracted.physical design cell is imported to StarRC [17] to extract RCparasitics. These extracted parasitics and post placement netlist are sent to PrimeTime for timing analysis and critical path extraction. These extracted critical paths are converted to TetraMAX [15] readable critical paths. In TetraMAX [15] stuckat faults are added to all the critical paths to check the functionality of each path. If any path is identified as nonfunctional, it is detected and set as a false path constraint in the PrimeTime [18]. This process of detecting false path and elimination of false path is done until all false paths are eliminated from the circuit. Design Total Critical paths (FF s) IV. IMPLEMENTATION AND RESULTS TABLEI. Number of critical paths before and after filtering technique Total False critical paths identified (FF s) STA critical pathdelay (ns) True Synthesizable critical path delay (ns) S35932 1728 28 13.39 ns 13.20 ns S15850 534 105 4.36 ns 4.25 ns S13207 638 52 2.85 ns 2.79 ns S9234 211 15 2.07 ns 2.03 ns S5378 179 13 1.59 ns 1.55 ns S1488 6 2 1.66 ns 1.60 ns S1423 74 50 5.22 ns 4.87 ns S1238 18 4 1.77 ns 1.74 ns S1196 18 3 2.03 ns 1.96 ns S832 32 0 1.89 ns 1.89 ns S820 16 0 2.90 ns 2.90 ns S400 21 10 1.15 ns 1.12 ns In the table I column shows critical and false critical paths of ISCAS 89 benchmark circuits and column 2 shows the total number of critical paths in the circuits. The corresponding critical false paths detected after functional path or synthesizable path analysis using TetraMAX [15] is also reported.sta reported critical paths with pathdelay and reported synthesizable critical path with pathdelay after filtering of false paths from the circuits are also reported. In S832 and S820 no false path is reported, hence STA critical path is the true critical path. TABLE II.Combinational circuits with total number of critical paths and false paths and true synthesizable critical path. Design Total critical paths (FF s) Total False critical paths identified (FF s) STA critical pathdelay (ns) True synthesizable critical path delay (ns) C432 44 11 3.12 3.02 C499 74 26 2.20 1.89 C2670 221 47 2.71 2.65 C6288 64 15 9.71 9.67 C1355 74 21 2.29 2.18 C5315 301 84 2.06 2.01 Table II shows the combinational ISCAS 85 benchmark circuits and the list of critical paths in the circuits. Number of false paths identified after functional path analysis usingtetramax [15] is also shown. STA PrimeTime reported critical paths with pathdelay and the reported synthesizable critical path with pathdelay after filtering of false paths from the circuits are also shown. DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2730

TABLE III.STA true critical path with STA false critical path for ISCAS 85 circuits. Circuit STA true Critical path STA critical path C432 3.10 3.12 C499 1.15 2.20 C2670 2.70 2.71 C6288 9.68 9.71 C1355 2.25 2.29 C5315 2.03 2.06 Static timing analysis tool PrimeTime[18] reported critical path and false critical paths for ISCAS 85 combinational circuits. Table shows the STA true critical path delay comparison with STA critical path. TABLE IV.STA true critical path with STA false critical path for ISCAS 89 circuits Circuit STA true Critical path (ns) STA critical path (ns) S35932 13.39 13.39 S15850 4.35 4.36 S13207 2.54 2.85 S5378 2.05 2.07 S1488 1.66 1.66 S1423 5.22 5.24 S1238 1.76 1.77 S1196 2.02 2.03 S832 1.89 1.89 S820 2.90 2.90 S400 1.14 1.15 From table IV it is evident that STA can report both critical path and true critical path delay but still its an estimate and accuracy is less. V. CONCLUSION Critical paths are important for any circuit analysis. All critical paths are not synthesizable. These nonsynthesizable critical paths are non-functional paths in the circuit. These non-functional paths are also called false paths. If any one false path is taken into consideration for circuit analysis, the result would be conservative and performance of the circuit will be affected. ISCAS 85 and ISCAS 89 circuits are considered for timing analysis. Static timing analysis reports the critical path and false path which are not accurate and the reported critical paths are may or may not be synthesizable. Also Static timing analysis cannot identify the number of false critical paths in the circuit. Dynamic simulation is the solution for false path identification. The proposed methodology identifies the number of false paths in the circuit through ATPG and false paths are eliminated through set false path constraints. REFERENCES [1] Jung, Jongyoon, and Taewhan Kim. "Variation-aware false path analysis based on statistical dynamic timing analysis." ComputeAidedDesign of Integrated Circuits and Systems, IEEE Transactions on 31.11 (2012): 1684-1697. [2] Wang, Sying-Jyan, Tsung-HueiTzeng, and Katherine Shi-Min Li. "Fast and accurate statistical static timing analysis." Circuits ansystems (ISCAS), 2014 IEEE International Symposium on. IEEE, 2014. [3] Xu, Jun, and Xiangku Li. "Improve accuracy of delay element by filtering false path for low power desychronized circuits." Circuitsand Systems (ISCAS), 2011 IEEE International Symposium on. IEEE, 2011 [4] Tsai, Shihheng, and Chung-Yang Huang. "A false-path aware formal static timing analyzer considering simultaneous inputransitionsdesign Automation Conference, 2009. DAC'09. 46th ACM/IEEE. IEEE, 2009. [5] Crouch, Alfred L., and John C. Potter. "Invited-A box of dots: using scan-based path delay test for timing verification." Proceedingsof the 53rd Annual Design Automation Conference. ACM, 2016. [6] Bell, Jeffrey L., K. Sakallah, and J. Whittemore. "False path analysis in sequential circuits." Proceedings of 8th International Workshopon Power and Timing Modeling, Optimization and Simulation. 2007 [7] Zeng, Jing, MagdyAbadir, and Jacob Abraham. "False timing path identification using ATPG techniques and delay-based information"design Automation Conference, 2002. Proceedings. 39th. IEEE, 2002. [8] Parnerkar, Shreyas Vijay. Timing False Path Identification using ATPG Techniques. Diss. University of Wisconsin. DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2731

[9] Bhaghath, P. J., and S. R. Ramesh. "A Survey of SSTA Techniques with Focus on Accuracy and Speed." International JournalofComputer Applications 89.7 (2014). [10] Bhaghath, P. J., and S. R. Ramesh. "A comparison on timing analysis using probabilistic approaches." Communications and SignalProcessing (ICCSP), 2014 International Conference on. IEEE, 2014. [11] Bhasker, Jayaram, and RakeshChadha. Static timing analysis for nanometer designs: a practical approach. Springer Science & BusinessMedia, 2009 [12] Synopsys Inc., IC Compiler Implementation User Guide Version L-2016.03, March 2016 [13] Synopsys Inc., Design Compiler User Guide Version L-2016.03, March 2016 [14] Synopsys Inc., HDL Compiler for Verilog User Guide Version J-2014.09, September2014 [15] Synopsys Inc., TetraMAX ATPG User Guide Version L-2016.03-SP1, April 2016 [16] Synopsys Inc., DFT Compiler, DFTMAX, and DFTMAX Ultra User Guide Version L-2016.03, March 2016 [17] Synopsys Inc., StarRC User Guide and Command Reference Version K-2015.12, December 2015 [18] Synopsys Inc., PrimeTime User Guide Version K-2015.12, December 2015 AUTHOR PROFILE Samarshekar R received the B.E degree in Electronics and instrumentation from B.V.Bhoomaraddi College of engineering, Hubli, India in 2013. He is currently a student perceiving Master degree in Amrita School of Engineering, Coimbatore, Amrita VishwaVidyapeetham, and Amrita University Coimbatore, India. His research interests are Static timing analysis and critical path and false path analysis. Ramesh.S R currently serves as an Assistant Professor with the Department of Electronics and Communication Engineering, Amrita VishwaVidyapeetham, Amrita University, India. He received his Master of Engineering in VLSI Design from ArulmiguKalasalingam College of Engineering (Anna University, Chennai ) in 2007 and Bachelor of Engineering in Electronics and Communication from Cape Institute of Technology (Anna University, Chennai) in 2005. His areas of interest include VLSI Design, Static Timing analysis, VLSI CAD, FPGA Logic Architectures and Embedded Sensor Networks. He is an Associate Member in IETE. DOI: 10.21817/ijet/2016/v8i6/160806231 Vol 8 No 6 Dec 2016-Jan 2017 2732