IRL8113 IRL8113S IRL8113L

Applications l High Frequency Synchronous Buck Converters for Computer Processor Power V DSS PD - 95821 IRL8113 IRL8113S IRL8113L HEXFET Power MOSFET R DS(on) max Qg (Typ.) 30V 6.0m: 23nC Benefits l l l Low R DS(on) at 4.5V V GS Low Gate Charge Fully Characterized Avalanche Voltage and Current TO-220AB IRL8113 D 2 Pak IRL8113S TO-262 IRL8113L Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 I D @ T C = 25 C Continuous Drain Current, V GS @ 10V 105 h A I D @ T C = 100 C Continuous Drain Current, V GS @ 10V 74 h I DM Pulsed Drain Current c 420 P D @T C = 25 C Maximum Power Dissipation 110 W P D @T C = 100 C Maximum Power Dissipation Linear Derating Factor 57 0.76 W/ C T J Operating Junction and -55 to 175 C T STG Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw f 300 (1.6mm from case) 10 lbfyin (1.1Nym) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case i 1.32 C/W R θcs Case-to-Sink, Flat Greased Surface f 0.50 R θja Junction-to-Ambient fi 62 R θja Junction-to-Ambient (PCB Mount) gi 40 Notes through are on page 12 www.irf.com 1 1/6/04

Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 0.020 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 4.8 6.0 mω V GS = 10V, I D = 21A e 5.7 7.1 V GS = 4.5V, I D = 17A e V GS(th) Gate Threshold Voltage 1.35 2.25 V V DS = V GS, I D = 250µA V GS(th) / T J Gate Threshold Voltage Coefficient -5.0 mv/ C I DSS Drain-to-Source Leakage Current 1.0 µa V DS = 24V, V GS = 0V 150 V DS = 24V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 100 na V GS = 20V Gate-to-Source Reverse Leakage -100 V GS = -20V gfs Forward Transconductance 86 S V DS = 15V, I D = 17A Q g Total Gate Charge 23 35 Q gs1 Pre-Vth Gate-to-Source Charge 6.0 V DS = 15V Q gs2 Post-Vth Gate-to-Source Charge 2.0 nc V GS = 4.5V Q gd Gate-to-Drain Charge 8.3 I D = 17A Q godr Gate Charge Overdrive 6.7 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 10 Q oss Output Charge 14 nc V DS = 16V, V GS = 0V t d(on) Turn-On Delay Time 14 V DD = 15V, V GS = 4.5V e t r Rise Time 38 I D = 17A t d(off) Turn-Off Delay Time 18 ns Clamped Inductive Load t f Fall Time 5.0 C iss Input Capacitance 2840 V GS = 0V C oss Output Capacitance 620 pf V DS = 15V C rss Reverse Transfer Capacitance 290 ƒ = 1.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 220 mj I AR Avalanche Currentc 17 A E AR Repetitive Avalanche Energy c 11 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 105 h (Body Diode) A I SM Pulsed Source Current 420 (Body Diode)c V SD Diode Forward Voltage 1.0 V t rr Reverse Recovery Time 18 27 ns Q rr Reverse Recovery Charge 7.2 11 nc Conditions V GS = 0V, I D = 250µA Conditions MOSFET symbol showing the integral reverse S p-n junction diode. T J = 25 C, I S = 17A, V GS = 0V e T J = 25 C, I F = 17A, V DD = 15V di/dt = 100A/µs e 2 www.irf.com G D

I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRL8113/S/L 1000 VGS TOP 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 1000 VGS TOP 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 100 100 3.0V 3.0V 10 60µs PULSE WIDTH Tj = 25 C 0.1 1 10 10 60µs PULSE WIDTH Tj = 175 C 0.1 1 10 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.0 I D = 42A V GS = 10V 100 1.5 T J = 175 C 10 T J = 25 C 1.0 V DS = 10V 60µs PULSE WIDTH 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 V GS, Gate-to-Source Voltage (V) 0.5-60 -40-20 0 20 40 60 80 100 120 140 160 180 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3

I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRL8113/S/L 100000 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 12 10 I D = 17A V DS = 24V VDS= 15V 10000 8 Ciss 6 1000 Coss 4 Crss 2 100 1 10 100 V DS, Drain-to-Source Voltage (V) 0 0 10 20 30 40 50 60 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 1000.0 100.0 10.0 1.0 T J = 175 C T J = 25 C V GS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V SD, Source-to-Drain Voltage (V) 10000 1000 100 10 OPERATION IN THIS AREA LIMITED BY R DS (on) 100µsec 1 Tc = 25 C Tj = 175 C 1msec Single Pulse 10msec 0.1 0.1 1.0 10.0 100.0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com

I D, Drain Current (A) V GS(th) Gate threshold Voltage (V) IRL8113/S/L 120 100 80 LIMITED BY PACKAGE 2.5 2.0 60 1.5 I D = 250µA 40 20 1.0 0 25 50 75 100 125 150 175 T C, Case Temperature ( C) 0.5-75 -50-25 0 25 50 75 100 125 150 175 T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 1 Thermal Response ( Z thjc ) 0.1 0.01 0.001 0.0001 D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) R 1 R 2 R 3 R 1 R 2 R 3 τ J τ J τ 1 τ τ 2 τ 3 1 τ 2 τ 3 Ci= τi/ri Ci= τi/ri 1E-006 1E-005 0.0001 0.001 0.01 0.1 t 1, Rectangular Pulse Duration (sec) τ C τ Ri ( C/W) τi (sec) 0.430 0.000266 0.397 0.000685 0.493 0.007393 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5

E AS, Single Pulse Avalanche Energy (mj) IRL8113/S/L R DS (on), Drain-to -Source On Resistance ( mω) 40 30 I D = 21A 1000 800 I D TOP 8.8A 11A BOTTOM 17A 600 20 400 10 T J = 125 C T J = 25 C 0 2.0 4.0 6.0 8.0 10.0 V GS, Gate-to-Source Voltage (V) Fig 12. On-Resistance Vs. Gate Voltage 200 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature ( C) Fig 13c. Maximum Avalanche Energy Vs. Drain Current 15V L D V DS R G V DS 20V V GS tp L D.U.T I AS 0.01Ω DRIVER - V DD A Fig 13a. Unclamped Inductive Test Circuit V GS Pulse Width < 1µs Duty Factor < 0.1% D.U.T V DD - tp V (BR)DSS Fig 14a. Switching Time Test Circuit V DS 90% 10% V GS I AS t d(on) t r t d(off) t f Fig 13b. Unclamped Inductive Waveforms Fig 14b. Switching Time Waveforms 6 www.irf.com

- D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =10V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Current Regulator Same Type as D.U.T. Vds Id Vgs 50KΩ 12V.2µF.3µF D.U.T. V - DS Vgs(th) V GS 3mA I G I D Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Test Circuit Fig 17. Gate Charge Waveform www.irf.com 7

Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f i g ( ) Q g V g f Q oss 2 V f in I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 Rds(on) ( ) Q g V g f Q oss 2 V in f Q rr V in f *dissipated primarily in Q1. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q1 turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8 www.irf.com

TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) - A - 4.69 (.185) 4.20 (.165) - B - 1.32 (.052) 1.22 (.048) 15.24 (.600) 14.84 (.584) 4 6.47 (.255) 6.10 (.240) 1 2 3 1.15 (.045) MIN LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 1.15 (.045) 3X 0.93 (.037) 0.69 (.027) 0.36 (.014) M B A M 0.55 (.022) 3X 0.46 (.018) 2.92 (.115) 2.64 (.104) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C For GB Production EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO PART NUMBER LOT CODE DATE CODE www.irf.com 9

D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" For GB Production THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE INTERNATIONAL RECTIFIER LOGO F530S F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L PART NUMBER LOT CODE DATE CODE 10 www.irf.com

TO-262 Package Outline Dimensions are shown in millimeters (inches) IGBT 1- GATE 2- COLLEC- TOR TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 INTERNATIONAL ASSEMBLED ON WW 19, 1997 RECTIFIER IN THE ASSEMBLY LINE "C" LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C www.irf.com 11

D 2 Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) 10.90 (.429) 10.70 (.421) 11.60 (.457) 11.40 (.449) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 1.58mH, R G = 25Ω, I AS = 21A. ƒ Pulse width 400µs; duty cycle 2%. This is only applied to TO-220AB pakcage. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 This is applied to D 2 Pak, when mounted on 1" square PCB (FR- 4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 42A. R θ is measured at T J approximately 90 C TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 1/04 12 www.irf.com

Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/