Galvanic Isolaed 8 Channel High-Side Swich Daashee Revision 2.4, 2014-10-20 Power Managemen & Mulimarke
Ediion 2014-10-20 Published by Infineon Technologies AG 81726 Munich, Germany 2014 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.
Revision Hisory Page or Iem Subjecs (major changes since previous revision) Revision 2.4, 2014-10-20 Page 4 Feaure lis updaed, Vbb Monioring included Page 7 Page 7 Chaper 2 Block diagram updaed Page 9 Page 9 Chaper 3.3.3 Descripion for repeiive shor circui correced Page 9 Page 9 Chaper 3.4 Vbb Monioring included in common diagnosic oupu descripion Page 16 Page 16 Chaper 4.5 Foonoes correced Page 18 Page 18 Chaper 4.8 Timing parameer for CS delay spli ino CSD and CSDMD Page 19 Page 19 Chaper 4.10 Parameer Minimum Inernal Gap removed all Correcion of formas and ypos Revision 2.3 Page 13 Page 13, Table 4.1 Exended operaing emperaure foonoe removed Revision 2.0 all Final Daashee Trademarks of Infineon Technologies AG AURIX, C166, CanPAK, CIPOS, CIPURSE, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, DI-POL, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EconoPACK, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalihIC, OpiMOS, ORIGA, POWERCODE ; PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SaRIC, SIEGET, SINDRION, SIPMOS, SmarLEWIS, SOLID FLASH, TEMPFET, hinq!, TRENCHSTOP, TriCore. Oher Trademarks Advance Design Sysem (ADS) of Agilen Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limied, UK. AUTOSAR is licensed by AUTOSAR developmen parnership. Blueooh of Blueooh SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirsGPS of Trimble Navigaion Ld. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsof Corporaion. FlexRay is licensed by FlexRay Consorium. HYPERTERMINAL of Hilgraeve Incorporaed. IEC of Commission Elecroechnique Inernaionale. IrDA of Infrared Daa Associaion Corporaion. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MahWorks, Inc. MAXIM of Maxim Inegraed Producs, Inc. MICROTEC, NUCLEUS of Menor Graphics Corporaion. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. muraa of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Sysems Inc. RED HAT Red Ha, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Saellie Radio Inc. SOLARIS of Sun Microsysems, Inc. SPANSION of Spansion LLC Ld. Symbian of Symbian Sofware Limied. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tekronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limied. VERILOG, PALLADIUM of Cadence Design Sysems, Inc. VLYNQ of Texas Insrumens Incorporaed. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zeex Limied. Las Trademarks Updae 2011-11-11 Daashee 3 Revision 2.4, 2014-10-20
Coreless Transformer Isolaed Digial Oupu 8 Channel 1.2 A High-Side Swich Produc Highlighs Coreless ransformer isolaed daa inerface Galvanic isolaion 8 High-side oupu swiches 1.2A µc compaible 8-bi serial peripheral Feaures Inerface CMOS 3.3/5V operaion compaible Serial Inerface High common mode ransien immuniy Shor circui proecion Maximum curren inernally limied Overload proecion Overvolage proecion (including load dump) Undervolage shudown wih auoresar and hyseresis Swiching inducive loads Common oupu disable pin Thermal shudown wih resar Thermal independence of separae channels Common diagnosic oupu ESD proecion Loss of GNDbb and loss of V bb proecion Very low sandby curren Reverse baery proecion Isolaed reurn pah for DIAG signal V bb monioring RoHS complian Typical Applicaion Isolaed swich for indusrial applicaions (PLC) All ypes of resisive, inducive and capaciive loads µc compaible power swich for 24V DC applicaions Driver for solenoid, relays and resisive loads Descripion The is a galvanically isolaed 8 bi daa inerface in PG-DSO-36 package ha provides 8 fully proeced high-side power swiches ha are able o handle currens up o 1.2 A. A serial µc compaible inerface allows o connec he IC direcly o a µc sysem. The inpu inerface is designed o operae wih 3.3/5V CMOS compaible levels. The daa ransfer from inpu o oupu side is realized by he inegraed Coreless Transformer Technology. Typical Applicaion VCC VCC Vbb Vbb VCC P1.x AD0 P0.0 P0.1 DIS CS SCLK SI Conrol Uni CT DIAG Conrol & Proecio n Uni OUT0 OUT1 Serial Inerface for daisy chain SO DIAG µc (i.e C166) OUT7 GND GNDCC GNDbb Type On-sae Resisance Package 200mΩ PG-DSO36 Daashee 4 Revision 2.4, 2014-10-20
Pin Configuraion and Funcionaliy 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion Pin Symbol Funcion 1 N.C. No conneced 2 VCC Posiive 3.3/5V logic supply 3 DIS Oupu disable 4 CS Chip selec 5 SCLK Serial Clock 6 SI Serial Daa inpu 7 N.C. No conneced 8 N.C. No conneced 9 N.C. No conneced 10 N.C. No conneced 11 N.C. No conneced 12 N.C. No conneced 13 SO Serial Daa Oupu 14 DIAG Common diagnosic oupu 15 GNDCC Inpu logic ground 16 N.C. No conneced 17 N.C. No conneced 18 N.C. No conneced 19 GNDbb Oupu driver ground 20 N.C No conneced 21 OUT7 High-side oupu of channel 7 22 OUT7 High-side oupu of channel 7 23 OUT6 High-side oupu of channel 6 24 OUT6 High-side oupu of channel 6 25 OUT5 High-side oupu of channel 5 26 OUT5 High-side oupu of channel 5 27 OUT4 High-side oupu of channel 4 28 OUT4 High-side oupu of channel 4 29 OUT3 High-side oupu of channel 3 30 OUT3 High-side oupu of channel 3 31 OUT2 High-side oupu of channel 2 32 OUT2 High-side oupu of channel 2 33 OUT1 High-side oupu of channel 1 34 OUT1 High-side oupu of channel 1 35 OUT0 High-side oupu of channel 0 36 OUT0 High-side oupu of channel 0 TAB Vbb Posiive driver power supply volage N.C. 1 VCC DIS 2 3 CS SCLK 4 5 SI 6 N.C. N.C. N.C. N.C. 7 8 9 10 N.C. 11 N.C. 12 SO 13 DIAG GNDCC 14 15 N.C. 16 N.C. N.C. Figure 1. 17 18 Vbb TAB TAB Vbb Power SO-36 (430mil) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 OUT6 OUT6 OUT7 OUT7 N.C. GNDbb Daashee 5 Revision 2.4, 2014-10-20
Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy VCC (Posiive 3.3/5V logic supply) The VCC supplies he inpu inerface ha is galvanically isolaed from he oupu driver sage. The inpu inerface can be supplied wih 3.3V / 5V. DIS (Oupu disable) The high-side oupus OUT0...OUT7 can be immediaely swiched off by means of he low acive pin DIS ha is an asynchronous signal. The inpu regisers are also rese by he DIS signal. The oupu remains swiched off afer low-high ransien of DIS, ill new daa is wrien ino he inpu inerface. Curren Sink o GNDCC CS (Chip selec) The sysem microconroller selecs he by means of he low acive pin CS o acivae he inerface. Curren Source o VCC GNDCC (Ground for VCC domain) This pin acs as he ground reference for he inpu inerface ha is supplied by VCC. GNDbb (Oupu driver ground domain) This pin acs as he ground reference for he oupu driver ha is supplied by Vbb. OUT0... OUT7 (High side oupu channel 0... 7) The oupu high side channels are inernally conneced o Vbb and conrolled by he corresponding daa inpu. TAB (Vbb, Posiive supply for oupu driver) The heaslug is conneced o he posiive supply por of he oupu inerface. SCLK (Serial shif clock) SCLK (serial clock) is used o synchronize he daa ransfer beween he maser and he. Daa presen a he SI pin are lached on he rising edge of he serial clock inpu, while daa a he SO pin is updaed afer he falling edge of SCLK. Curren Source o VCC SI (Serial daa inpu) This pin is used o ransfer daa ino he device. Daa is lached on he rising edge of he serial clock. Curren Sink o GNDCC SO (Serial daa oupu) SO can be conneced o a serial inpu of a furher IC o build a daisy-chain configuraion. I is only acvaed if CS is in low sae, oherwise his oupu is in high impedance sae. DIAG (Common diagnosic oupu) The low acive DIAG signal conains he OR-wired informaion of he separaed overemperaure deecion unis for each channel.the oupu pin DIAG provides an open drain funcionaliy. A curren source is also conneced o he pin DIAG. In normal operaion he signal DIAG is high. When overemperaure or Vbb below ON-Limi is deeced he signal DIAG changes o low. Daashee 6 Revision 2.4, 2014-10-20
Blockdiagram 2 Blockdiagram CS SCLK SI SO Undervolage Shudown wih Resar Serial Inpu Inerface Logic CT Serial o Parallel Undervolage Shudown wih Resar o Logic Channel 1-6 Logic Charge Pump Level shifer Recifier High-side Channel 0 o Logic Channel 1-6 Common Diagnosic Oupu Logic Charge Pump Level Shifer Recifier High-side Channel 7 Volage Source Overvolage Proecion Limiaion of Unclamped Inducive Load Curren Limiaion Overload Proecion Temperaure Sensor from Temperaure Sensor Channel 1-6 Channel 1... 6 Limiaion of Unclamped Inducive Load Curren Limiaion Overload Proecion Temperaure Sensor Vbb Vbb GNDbb OUT0 OUT7 Galvanic Isolaion VCC GNDCC DIS DIAG VCC 100µA Undervolage Gae Proecion Gae Proecion OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Figure 2 Blockdiagram Daashee 7 Revision 2.4, 2014-10-20
Funcional Descripion 3 Funcional Descripion 3.1 Inroducion The ISOFACE includes 8 high-side power swiches ha are conrolled by means of he inegraed µc compaible SPI inerface. The oupus OUT0...OUT7 are conrolled by he daa of he serial inpu SI. The IC can replace 8 opocouplers and he 8 high-side swiches in convenional I/O-Applicaions as a galvanic isolaion is implemened by means of he inegraed coreless ransformer echnology. The µc compaible inerface allows a direc connecion o he pors of a microconroller wihou he need for oher componens. Each of he 8 high-side power swiches is proeced agains shor o Vbb, overload, overemperaure and agains overvolage by an acive zener clamp. The diagnosic logic on he power chip recognizes he overemperaure informaion of each power ransisor The informaion is send via he inernal coreless ransformer o he pin DIAG a he inpu inerface. 3.2 Power Supply The IC conains 2 galvanic isolaed volage domains ha are independen from each oher. The inpu inerface is supplied a VCC and he oupu sage is supplied a Vbb. The differen volage domains can be swiched on a differen ime. The oupu sage is only enabled once he inpu sage eners a sable sae. 3.3.2 Power Transisor Overvolage Proecion Each of he eigh oupu sages has is own zener clamp ha causes a volage limiaion a he power ransisor when solenoid loads are swiched off. V ON is hen clamped o 47V (min.). Vz GNDbb Figure 3 Inducive and overvolage oupu clamp (each channel) Energy is sored in he load inducance during an inducive load swich-off. 2 E L = 1 2 L I L E bb Vbb OUTx E AS V ON Vbb 3.3 Oupu Sage Each channel conains a high-side verical power FET ha is proeced by embedded proecion funcions. The coninuous curren for each channel is 1.2A (all channels ON). V bb Dx Vbb GNDbb OUTx Z L L R L E Load E L E R 3.3.1 Oupu Sage Conrol Each oupu is independenly conrolled by an oupu lach and a common rese line via he pin DIS ha disables all eigh oupus and reses he laches. Serial daa inpu (SI) is read on he rising edge of he serial clock SCLK. A logic high inpu daa bi urns he respecive oupu channel ON, a logic low daa bi urns i OFF. CS mus be low whils shifing all he serial daa ino he device. A low-o-high ransiion of CS ransfers he serial daa inpu bis o he oupu buffer. Figure 4 Inducive load swich-off energy dissipaion (each channel) While demagneizing he load inducance, he energy dissipaion in he DMOS is E AS = E bb + E L E R = V ON( CL) i L ()d wih an approximae soluion for R L > 0Ω:: I L L I E AS ( V 2 R bb + V ON( CL) ) 1 L R = ln + L L V ON( CL) Daashee 8 Revision 2.4, 2014-10-20
Funcional Descripion 3.3.3 Power Transisor Overcurren Proecion IN The oupus are provided wih a curren limiaion ha eners a repeiive swiched mode afer an iniial peak curren has been exceeded. The iniial peak shor circui curren limi is se o I L(SCp) a T j = 125 C. During he repeiive shor circui he curren limi is se o I L(SCr). If his operaion leads o an overemperaure condiion, a second proecion level (T j > 135 C) will change he oupu ino a low duy cycle PWM (selecive hermal shudown wih resar) o preven criical chip emperaures. IN VOUT I L DIAG Normal operaion Oupu shor o GND I L(SCp) IL(SCr) VOUT T J Figure 7 Shor circui in on-sae, shu down down by overemperaure, resar by cooling 3.4 Common Diagnosic Oupu DIAG Figure 5 Overemperaure deecion The following figures show he iming for a urn on ino shor circui and a shor circui in on-sae. Heaing up of he chip may require several milliseconds, depending on exernal condiions. IN The overemperaure deecion informaion are ORwired in he common diagnosic oupu block. The informaion is send via he inegraed coreless ransformer o he inpu inerface. In addiion Vbb undervolage is indicaed a he DIAG oupu. The oupu sage a pin DIAG has an open drain funcionaliy combined wih a curren source. DIAG VCC 100µA CT Common Diagnosic Oupu VOUT Oupu shor o GND I L I L(SCp) IL(SCr) DIAG Figure 8 Common diagnosic oupu Figure 6 Turn on ino shor circui, shu down by overemperaure, resar by cooling Daashee 9 Revision 2.4, 2014-10-20
Funcional Descripion 3.5 Serial Inerface The conains a serial inerface ha can be direcly conrolled by he microconroller oupu pors. 3.5.1 SPI Signal Descripion CS - Chip selec. The sysem microconroller selecs he by means of he CS pin. Whenever he pin is in a logic low sae, daa can be ransferred from he µc. CS High o low ransiion: SI - Serial inpu. Serial daa bis are shifed in a his pin, he mos significan bi firs. SI informaion is read in on he rising edge of he SCLK. Inpu daa is lached in he shif regiser and hen ransferred o he conrol buffer of he oupu sages. SO - Serial oupu. SO is in a high impedance sae unil he CS pin goes o a logic low sae. The daa of he inernal shif regiser are shifed ou serially a his pin. The mos significan bi will appear a firs. The furher bis will appear following he falling edge of SCLK. 3.5.2 SPI Bus Conceps Serial inpu daa can be clocked in from hen on SO changes from high impendance sae o logic high or low sae corresponding o he SO bi-sae CS Low o high ransiion: Transfer of SI bis from shif regiser ino oupu buffers, if number of clock signals was an ineger muliple of 8 SO changes from he SO bi-sae o high impendance sae To avoid any false clocking he serial inpu pin SCLK should be logic high sae during high-o-low ransiion of CS. When CS is in a logic high sae, any signals a he SCLK and SI pins are ignored and SO is forced ino a high impedance sae. The inegraed modulo couner ha couns he number of clocks avoids he ake over of invalid commands caused by a spike on he clock line or wrong number of clock cycles. A command is only aken over, if afer he low-o-high ransiion of he CS signal he number of couned clock cycles is recognized as a muliple of 8. SCLK - Serial clock. The sysem clock pin clocks he inernal shif regiser of he. The serial inpu (SI) acceps daa ino he inpu shif regiser on he rising edge of SCLK while he serial oupu (SO) shifs he oupu informaion ou of he shif regiser on he falling edge of he serial clock. I is essenial ha he SCLK pin is in a logic high sae whenever chip selec CS makes any ransiion. The number of clock pulses will be couned during a chip selec cycle. The received daa will only be acceped, if exacly an ineger muliple of 8 clock pulses were couned during CS is acive. 3.5.2.1 Independen Individual Conrol Each IC wih a SPI is conrolled individually and independenly by an SPI maser, as in a direcional poin-o-poin communicaion.the por requiremens for his opology are he greaes, because for each conrolled IC an individual SPI a he µc is needed (SCLK, CS, SI). All ICs can be addressed simulaneously wih he full SPI bandwidh. SPI 1 SPI n µc Figure 9 CLK Tx a1 Tx a2 CLK Tx n1 Tx n2 SCLK CS SI SO SPI - Inerface IC1 SCLK CS SI SO SPI - Inerface ICn Number of adressed ICs = n Number of necessary conrol and daa pors = 3 n Individual ICs are adressed by he chip selec Oupu lines Oupu lines Individual independen conrol of each IC wih SPI Daashee 10 Revision 2.4, 2014-10-20
Funcional Descripion 3.5.2.2 Daisy-chain Configuraion The connecion of differen ICs and a µc as shown in Fig. 10 is called a daisy-chain. For his ype of busopology only one SPI inerface of he µc for wo or more ICs is needed. All ICs share he same clock and chip selec por of he SPI maser. Tha is all ICs are acive and addressed simulaneously. The daa ou of he µc is conneced o he SI of he firs IC in he line. Each SO of an IC is conneced o he SI of he nex IC in he line. 3.6 Transmission Failure Deecion There is a failure deecion uni inegraed o ensure also a sable funcionaliy during he inegraed coreless ransformer ransmission. This uni decides wheher he ransmied daa is valid or no. If four imes serial daa coming from he inernal regisers is no acceped he oupu sages are swiched off unil he nex valid daa is received. SPI 1 CLK Tx a1 Tx a2 SCLK CS SI SO Oupu lines SPI - Inerface IC1 SCLK CS SI Oupu lines SPI - Inerface µc ICn Number of adressed ICs = n Number of necessary conrol and daa pors = 3 All ICs are adressed by he common chip selec Figure 10 SPI bus all ICs in a daisy chain configuraion The µc feeds he daa bis ino he SI of IC1 (firs IC in he chain). The bis coming from he SO of IC1 are direcly shifed ino he SI of he nex IC. As long as he chip selec is inacive (logic high) all he IC SPIs ignore he clock (SCLK) and inpu signals (SI) and all oupus (SO) are in risae. As long as he chip selec is acive he SPI regiser works as a simple shif regiser. Wih each clock signal one inpu is shifed ino he SPI regiser (SI), each bi in he shif regiser moves one posiion furher wihin he regiser, and he las bi in he SPI shif regiser is shifed ou of SO. This is coninued as long as he chip selec is acive (logic low) and clock signals are applied. The daa is hen only aken over o he oupu buffers of each IC when he CS signal changes o high from low and recognized as valid daa by he inernal modulo couner. Daashee 11 Revision 2.4, 2014-10-20
Funcional Descripion 3.7 Serial Inerface Timing CS Chip selec acive SCLK SI n+7 n+6 n+5 n+4 n+3 n+2 n+1 n SO n n-1 n-2 n-3 n-4 n-5 n-6 n-7 Figure 11 Serial inerface CS p(sclk) CSS CSH CSD SCLK SI Figure 12 SU HD MSB In Serial inpu iming diagram LSB In CS SCLK VALID SODIS SO MSB Ou LSB Ou Figure 13 Serial oupu iming diagram Daashee 12 Revision 2.4, 2014-10-20
4 Elecrical Characerisics Elecrical Characerisics Noe: All volages a pins 2 o 14 are measured wih respec o ground GNDCC (pin 15). All volages a pin 20 o pin 36 and TAB are measured wih respec o ground GNDbb (pin 19). The volage levels are valid if oher raings are no violaed. The wo volage domains V CC,GND CC and V bb,gnd bb are inernally galvanically isolaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 2 (VCC) and TAB (Vbb) is discharged before assembling he applicaion circui. Supply volages higher han V bb(az) require an exernal curren limi for he GNDbb pin, e.g. wih a 15Ω resisor in GNDbb connecion. Operaing a absolue maximum raings can lead o a reduced lifeime. Parameer Symbol Limi Values Uni a T j = -40... 135 C, unless oherwise specified min. max. Supply volage inpu inerface (VCC) V CC -0.5 6.5 V Supply volage oupu inerface (Vbb) V bb -1 1) 45 Coninuos volage a pin SI V SI -0.5 6.5 Coninuos volage a pin CS V CS -0.5 6.5 Coninuos volage a pin SCLK V SCLK -0.5 6.5 Coninuos volage a pin DIS V DIS -0.5 6.5 Coninuos volage a pin SO V SO -0.5 6.5 Coninuos volage a pin DIAG V DIAG -0.5 6.5 Load curren (shor-circui curren) I L self limied A Reverse curren hrough GNDbb 1) I GNDbb -1.6 Operaing Temperaure T j -25 inernal limied C Exended Operaion Temperaure T j -40 inernal limied Sorage Temperaure T sg -50 150 Power Dissipaion 2) P o 3.3 W Inducive load swich-off energy dissipaion 3) single pulse, T j = 125 C, I L = 1.2A one channel acive all channel simulaneously acive (each channel) Load dump proecion 3) V loaddump 4) =V A + V S V IN = low or high d = 400ms, R I = 2W, R L = 27W, V A = 13.5V d = 350ms, R I = 2W, R L = 57W, V A = 27V 1) defined by P o 2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 wih 6cm² (one layer, 70µm hick) copper area for drain connecion. PCB is verical wihou blown air. 3) no subjec o producion es, specified by design 4) V Loaddump is seup wihou he DUT conneced o he generaor per ISO7637-1 and DIN40839 E AS V Loaddump 10 1 V V Elecrosaic discharge volage (Human Body Model) kv according o JESD22-A114-B ESD 2 Elecrosaic discharge volage (Charge Device Model) kv according o ESD STM5.3.1-1999 ESD 1 Coninuos reverse drain curren 1)3), each channel I S 4 A 90 117 J V Daashee 13 Revision 2.4, 2014-10-20
Elecrical Characerisics 4.2 Thermal Characerisics Parameer Symbol Limi Values Uni Tes Condiion a T j = -25... 125 C, V bb =15...30V, V CC = 3.0...5.5V, unless oherwise specified min. yp. max. Thermal resisance juncion - case R hjc 1.5 K/W Thermal resisance @ min. fooprin R h(ja) 50 Thermal resisance @ 6cm² cooling area 1) R h(ja) 38 1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 wih 6cm² (one layer, 70µm hick) copper area for drain connecion. PCB is verical wihou blown air. 4.3 Load Swiching Capabiliies and Characerisics Parameer a T j = -25... 125 C, V bb =15...30V, V CC = 3.0...5.5V, unless oherwise specified On-sae resisance, I L = 0.5A, each channel T j = 25 C T j = 125 C wo parallel channels, T j = 25 C: 1) four parallel channels, T j = 25 C: 1) Nominal load curren Device on PCB 38K/W, T a = 85 C, T j < 125 C one channel: 1) wo parallel channels: 1) four parallel channels: 1) 2) Turn-on ime o 90% V OUT R L = 47Ω, V Dx = 0 o 5V 1) Turn-off ime o 10% V OUT R L = 47Ω, V Dx = 5 o 0V Slew rae on 10 o 30% V OUT R L = 47Ω, V bb = 15V Slew rae off 70 o 40% V OUT R L = 47Ω, V bb = 15V 1) no subjec o producion es, specified by design Symbol Limi Values Uni Tes Condiion min. yp. max. R ON 150 270 75 38 200 320 100 50 mω L(NOM) 1.4 2.2 4.4 on 64 120 µs off 89 170 dv/d on 1 2 V/µs -dv/d off 1 2 2) The urn-on and urn-off ime includes he swiching ime of he high-side swich and he ransmission ime via he coreless ransformer in normal operaing mode. During a failure on he coreless ransformer ransmission urn-on or urn-off ime can increase by up o 50µs. A Daashee 14 Revision 2.4, 2014-10-20
Elecrical Characerisics 4.4 Operaing Parameers Parameer Symbol Limi Values Uni Tes Condiion a T j = -25... 125 C, V bb =15...30V, V CC = 3.0...5.5V, unless oherwise specified min. yp. max. Common mode ransien immuniy 1) ΔV ISO /d -25-25 kv/µs ΔV ISO = 500V Magneic field immuniy 1) H IM 100 A/m IEC61000-4-8 Volage domain V bb Operaing volage V bb 11 35 V (Oupu inerface) Undervolage shudown V bb(under) 7 10.5 Undervolage resar V bb(u_rs) 11 Undervolage hyseresis ΔV bb(under) 0.5 Undervolage curren I bb(uvlo) 1 2.5 ma V bb < 7V Operaing curren I GNDL 10 14 ma All Channels ON - no load Leakage oupu curren (included in I bb(off) ) V Dx = low, each channel I L(off) 5 30 µa Volage domain V CC Operaing volage V CC 3.0 5.5 V (Inpu inerface) Undervolage shudown V CC(under) 2.5 2.9 Undervolage resar V CC(u_rs) 3 Undervolage hyseresis ΔV CC(under) 0.1 Undervolage curren I CC(uvlo) 1 2 ma V cc < 2.5V Operaing curren I CC(on) 4.5 6 ma 1) no subjec o producion es Daashee 15 Revision 2.4, 2014-10-20
Elecrical Characerisics 4.5 Oupu Proecion Funcions Parameer 1) a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Iniial peak shor circui curren limi, each channel T j = -25 C, V bb = 30V, m = 700µs T j = 25 C T j = 125 C wo parallel channels: 2) four parallel channels: 2) Repeiive shor circui curren limi T j = T j (see iming diagrams) each channel: 2) wo parallel channels: 2) four parallel channels: 2) Symbol Limi Values Uni Tes Condiion min. yp. max. I L(SCp) 1.4 I L(SCr) 1) Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuos repeiive operaion. 2) no subjec o producion es, specified by design 3.0 4.5 wice he curren of one channel four imes he curren of one channel Oupu clamp (inducive load swich off) 3) a V OUT = V bb - V ON(CL) V ON(CL) 47 53 60 V Overvolage proecion V bb(az) 47 2) 4) Thermal overload rip emperaure T j 135 C Thermal hyseresis 2) ΔT j 10 K 3) If channels are conneced in parallel, oupu clamp is usually accomplished by he channel wih he lowes V ON(CL) 4) Higher operaing emperaure a normal funcion for each channel available 2.2 2.2 2.2 A 4.6 Diagnosic Characerisics a pin DIAG Parameer a T j = -25... 125 C, V bb =15...30V, V CC =3.0...5.5V, unless oherwise specified Common diagnosic sink curren (overemperaure of any channel) T j = 135 C Symbol Limi Values Uni Tes Condiion min. yp. max. I diagsink 5 ma V DIAGON < 0.25 x VCC Common diagnosic source curren I diagsource 100 µa Daashee 16 Revision 2.4, 2014-10-20
Elecrical Characerisics 4.7 Inpu Inerface Parameer a T j = -25... 125 C, V bb =15...30V, V CC = 3.0...5.5V, unless oherwise specified Inpu low sae volage (SI, DIS, CS, SCLK) Inpu high sae volage (SI, DIS, CS, SCLK) Inpu volage hyseresis (SI, DIS, CS, SCLK) Oupu low sae volage (SO) Oupu high sae volage (SO) Inpu pull down curren (SI, DIS) Inpu pull up curren (CS, SCLK) Oupu disable ime (ransiion DIS o logic low) 1)2) Normal operaion Turn-off ime o 10% V OUT R L = 47Ω Oupu disable ime (ransiion DIS o logic low) 1)2)3) Disurbed operaion Turn-off ime o 10% V OUT R L = 47Ω Symbol Limi Values Uni Tes Condiion min. yp. max. V IL -0.3 0.3 x V CC V IH 0.7 x V CC + V CC 0.3 V IHys 100 mv V OL -0.3 0.25 x V CC V C L < 50pF, R L > 10kΩ V OH 0.75 x V CC + V CC 0.3 I Idown 100 µa -I Iup 100 DIS 85 170 µs DIS 230 1) The ime includes he urn-on/off ime of he high-side swich and he ransmission ime via he coreless ransformer. 2) If Pin DIS is se o low he oupus are se o low; afer DIS se o high a new wrie cycle is necessary o se he oupu again. 3) The parameer is no subjec o producion es - verified by design/characerizaion V Daashee 17 Revision 2.4, 2014-10-20
Elecrical Characerisics 4.8 SPI Timing Parameer Symbol Limi Values Uni Tes Condiion a T j = -25... 125 C, V bb =15...30V, V CC = 3.0...5.5V, unless oherwise specified min. yp. max. Serial clock frequency f SCLK DC 20 MHz Serial clock period (1/fclk) p(slck) 50 ns CS Seup ime (falling edge of CS o falling edge of CSS 5 SCLK) CS Hold ime (rising edge of SCLK o rising edge CSH 10 of CS) CS Disable ime (CS high ime beween wo CSD 10 accesses) Daa seup ime (required ime SI o rising edge of SU 6 SCLK) Daa hold ime (falling edge of SCLK o SI) HD 6 SO Oupu valid ime VALID CL = 50pF 20 SO Oupu disable ime SODIS 20 ns Delay o nex CS cycle for muliple device synchronizaion 1) CSDMD 20 µs 2) Inpu o oupu daa ransmission jier IOJ 8 20 2) 1) necessary CS delay ime o ensure a proper daa updae for muliple devices 2) no subjec o producion es, specified by design 4.9 Reverse Volage Parameer a T j = -25... 125 C, V bb =15...30V, V CC = 3.0...5.5V, unless oherwise specified Reverse volage 1)2) R GND = 0 Ω R GND = 150 Ω Diode forward on volage IF = 1.25A, V Dx = low, each channel 1) defined by P o 2) no subjec o producion es, specified by design Symbol Limi Values Uni Tes Condiion min. yp. max. -V bb 1 45 -V ON 1.2 V Daashee 18 Revision 2.4, 2014-10-20
Elecrical Characerisics 4.10 Isolaion and Safey-Relaed Specificaion Parameer Value Uni Condiions Raed dielecric isolaion volage V ISO 500 V AC 1 - minue duraion 1) Shor erm emporary overvolage 1250 V 5s acc. DIN EN60664-1 1) Minimum exernal air gap (clearance) 2.6 mm shores disance hrough air. Minimum exernal racking (creepage) 2.6 mm shores disance pah along body. 1) no subjec o producion es, verified by characerizaion; Producion Tes wih 1100V, 100ms duraion 4.11 Reliabiliy For Qualificaion Repor please conac your local Infineon Technologies office! Daashee 19 Revision 2.4, 2014-10-20
Elecrical Characerisics Daashee 20 Revision 2.4, 2014-10-20
Elecrical Characerisics Daashee 21 Revision 2.4, 2014-10-20
Package Oulines 5 Package Oulines PG-DSO-36 (Plasic Dual Small Ouline Package) 1.1 ±0.1 +0.1 0 ±0.1 3.25 3.5 MAX. 11 ±0.15 1) 2.8 B +0.07-0.02 0.25 ±3 5 0.25 0.65 +0.13 15.74 ±0.1 (Heaslug) 36x 0.25 M 0.1 C ABC 1.3 6.3 (Mold) 14.2 ±0.3 Heaslug 0.95 ±0.15 0.25 B Boom View Index Marking 36 19 19 36 3.2 ±0.1 (Meal) 5.9 ±0.1 (Meal) 1 x 45 1 18 15.9 ±0.1 (Mold) 1) A 10 1 13.7-0.2 (Meal) Heaslug Figure 14 PG-DSO36 1) Does no include plasic or meal prorusion of 0.15 max. per side gps09181_1 Daashee 22 Revision 2.4, 2014-10-20
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