Decoupling capacitor placement

Decoupling capacitor placement

Covered in this topic: Introduction Which locations need decoupling caps? IC decoupling Capacitor lumped model How to maximize the effectiveness of a decoupling cap Parallel resonance in adjacent capacitors Sample decoupling capacitor placements Global decoupling benefits

Which circuit locations need decoupling caps? Decoupling can be used in several ways such as: 1. A process of separating one circuit from affecting the other circuit 2. A method of filtering power supply and digital noise 3. A way of providing a local energy bank that is large enough to maintain the supply level within the operating voltage level of any ICs or circuits during transient scenarios From the above definitions, it is now easy to determine which circuits need decoupling capacitors!

Power supply decoupling o The purpose of C1 in below circuit is to make the current loop area small so that the radiated and conducted emissions are minimized. High di/dt LDO High di/dt Decouple noise to ground Q1 and D1 are noisy devices with high di/dt. C1 decouples the harmonic content from other circuits and at the same time minimizes the radiation loop area that can cause EMI issues.

Single event decoupling In this circuit, C1 is a decoupling capacitor who s purpose it is to prevent the IC over voltage protection from false trigger during surge testing. In the earlier version of the design, this IC triggers due to transient on the OVP feature during common mode surge test. Surge testing is part of immunity test for power supplies. A voltage as high as 2kV-4kV is injected in the AC line for a short duration of time (in the order of microseconds). During this testing, sensitive devices can be affected and there is a need for decoupling capacitors. After installing C1 and a series resistor, the false trigger issue was cured.

Every IC Power and ground pin needs a decap It is good practice to provide at least one decoupling capacitor for every power and ground pin of an IC. MCU, DSC, DSP or any ICs require supply rails to be stable within operating voltage range. Decoupling capacitors will also bypass any unwanted high frequency noise riding on the supply lines to the ground.

Which circuit locations need decoupling caps? To limit noise propagation and minimize current loops: Power supply inputs Power supply outputs Every IC PWR/ pin pair Sprinkled over PCB with on X*Y grid Signals just before they go onto external cabling Power rails just before they go onto external cabling Signals and power rails that are connected to other PCBs via cabling Anywhere that you need to decouple noise

Comparing Ideal and Real Decoupling Network Ideal Decoupling Real Decoupling This is an ideal decoupling network This is a real decoupling network PCB trace resistance PCB trace inductance ESR ESL Ideal cap

Widen the low impedance band Impedance Resonant frequency Based from the impedance plot on the left, at frequencies below the series resonance the dominating factor is the capacitance. The impedance is inversely proportional to the capacitance. At frequencies above resonance, the dominating factor is the inductance wherein the impedance is directly proportional to it. The lowest impedance is obtain at the resonance frequency wherein it is only dictated by the ESR. Frequency Below resonance Above resonance

Effect of parasitic inductance on decoupling effecitveness Data properties 30pF load 2ns rise time 3v3 Current: 49.5mA per data line 792mA for 16 bit bus (max) Capacitance: 3v3 tolerance = 10% = 0.33V Select max droop = 50mV C = 32nF I = C (dv/dt) C = I (dt/dv) Voltage glitch 1.5 nh series parasitic inductance 792 ma peak 2ns rise time = 594 mv V = L (di/dt)

Parallel capacitor effect on resonance Impedance Total capacitance increase with parallel caps. Impedance decreases Resonant frequency Total inductance decreases with parallel caps. Impedance decreases Two capacitors in parallel Total ESR decrease with parallel caps Frequency Below resonance Above resonance

Widen the low impedance band Z eff (Ω) 1 x 100nF Z eff (Ω) 1 x 10nF 1 x 1nF 1 x 100nF 10 x 100nF Overall Impedance 0.1 0.3 1 3 10 30 300 1000 Freq (MHz) 0.1 0.3 1 3 10 30 300 1000 Freq (MHz) Decoupling caps in parallel (Same value) Decoupling caps in parallel (Different values)

Optimal bypass routing (1) (2) (3) (4) Optional Ferrite (5) (6) (7)

Decaps placement below high pin count ICs Capacitor d Top Layer Ground Plane h Power Plane Often no room on top layer Sometimes the minimum parasitic inductance is to place the decoupling caps directly below the IC Caps are placed between breakout vias Track inductance replaced with via inductance (use Saturn PCB calculator to figure out via inductance)

Parallel bypass routing 100nF 100nF 100nF Option 1 Option 2 ~5nH ~0.5nH

Power supply decoupling for minimium emissions Decoupling capacitors Wrong placement. Large current loop! Much better placement. Smaller current loop!

Global decoupling Global decoupling differs with the local decoupling because it is not intended to decouple a particular IC pin. 1. Helps to keep PDN impedance low over large area due to parallel ESL (effective <400 MHz) 2. Add distributed capactiance to decouple stray currents (accidental loops) 3. Keep same values recommended to avoid resonances EMSCAN - detect current distribution on a PCB

Summary What we ve covered: Which locations need decoupling caps? How to maximize the effectiveness of a decoupling cap Parallel resonance in adjacent capacitors Sample decoupling capacitor placements Optimal via locations Decoupling for high density BGA devices Global decoupling benefits