epartent of Electrical and oputer Engineering Fall 1 Lab 5: ifferential plifier. 1. OBJETIVES Explore the operation of differential FET aplifier with resistive and active loads: Measure the coon and differential ode open circuit voltage gains; Measure the frequency response of gains and coon ode rejection ratio.. INTOUTION.1. ifferential pair. In this lab we will study the basics of operation of differential aplifier. The heart of differential aplifier is differential pair coposed of two transistors. In our case it will be two NMOS transistors (fro L115). We will bias both of these NFETs using NMOS current irror like in previous labs (ade of 47 NFETs). Figure 1 shows the circuit with no signal applied and no load connected. V Figure 1. In this circuit and NFETs are differential pair that is biased by - current irror. s long as and are identical and have identical resistors in their drain circuits the differential pair branches are indistinguishable fro each other and should each take ½ of I bias. Hence and are biased by ½ of I bias and should have corresponding (identical) gate transconductance and output resistance. learly, the task of biasing is alost exactly the sae as in case of S aplifier only now we need to have twice bigger I bias. oon ode operation is when input signal is applied to both gates of and siultaneously. Figure shows this case. For the syetric branches and ideal current source bias (I bias ) the and drain currents cannot be changed. V V3 V4 Figure. 1
epartent of Electrical and oputer Engineering Fall 1 Then no response to coon ode excitation can be expected at either of branches (see operation of current source biased S aplifier without any source bypass capacitor). In this ideal case drain signal voltages in both and branches are zero. When the realistic current source bias is considered ( has finite output resistance) then soe slight variation of the branch currents are possible and soe signal can appear at drains of and. gain, it is expected to be sall like in case of S aplifier without any source bypass capacitor. learly, for perfectly syetric differential pair one can expect V 3 = V 4. If the output is taken as a difference between drain voltages of and then the response to coon ode excitation is going to be zero. In reality, there is always soe isatch between branches in differential pair and soe difference between V 3 and V 4 can arise. The aount of output signal that appears in response to coon ode excitation is characterized by V3 - V4 coon ode voltage gain:. (1) gain, ideally is zero and becoes nonzero only due to branch isatch and finite output resistance of bias current source. learly, this logic is applicable to properly biased transistors, in our case we need to keep all transistors in saturation; hence there is always a liit on aplitude of input signal that can be tolerated. ifferential ode operation is when input signal is applied as a difference between gates of and. Figure 3 circuit illustrates this case. V V3 V4 Figure 3. Now the input signal changes gate voltages at and out-of-phase. We can visualize positive excitation as: ½ of it increasing V G4 above zero and ½ of it decreasing V G3 below zero. Hence, pure differential input corresponds to identical in aplitude but out-of-phase excitation of two branches of differential pair. Under input signal applied the drain currents in two branches change for the sae aount but with different polarity. In exaple above, I 4 will increase above ½ I bias and I 3 will decrease below ½ I bias in response to positive half wave of differential input. onsequently, the V 4 will decrease below and V 3 will increase above their respective bias value (in ideal syetric syste these biases are the sae, of course). Since su of drain currents flowing through and should reain equal to I bias (sall difference can only arise due to finite output resistance of ), the signal voltages at drains of and are equal in aplitude but out-ofphase. The aount of output signal that appears in response to differential ode excitation is characterized by V3 - V4 differential ode voltage gain: g r. () oon ode rejection ration is defined as: M. (3)
epartent of Electrical and oputer Engineering Fall 1.. Single ended output. It is often desired to take output not differentially but fro single end, i.e. fro the drain of one of the g or transistor with respect to ground. In that case the would decrease twice (, r is ignored) since only half of the input is being used to generate what is now called the output voltage. M can degrade since the output resistance of ( r ) atters in single ended output case. oon ode voltage gain becoes. and M g r r learly, there is no need to have in both branches of differential pair if only single ended output operation is expected. Naely, if the output is to be taken fro drain of, then in drain of can be eliinated (Figure 4a). V (a) Figure 4. If the input is also expected to be in single ended for one can ground the gate of one of transistors in differential pair, for instance, gate of. This type of connection is neither pure differential nor pure coon ode but ixture of the. OM VG4 VG3 oon ode part of input signal can be calculated as:, (4) IF and differential ode part of input signal is: VG4 VG3. (5) Now the expected single ended output voltage is: IF OM g r, (6) since is often <<. It should be noted that it does not atter what gate is grounded. We could very well ground gate of and apply signal to gate of and would collect output voltage fro drain of. Only sign of the gain would change (Equation 6). learly, the single ended gain of differential aplifier with resistive load is liited by the sae considerations as in case of S aplifier..3. ctive load. ctive load is expected to iprove the differential ode voltage gain a lot. Figure 5 shows the scheatic of the differential aplifier with active load. Firstly, the active load current irror action will get rid of factor of two in denoinator of equation 6, i.e. increasing gain twofold. Secondly, the will be effectively replaced 3 V (b)
epartent of Electrical and oputer Engineering Fall 1 with output resistance of an active load transistor, thus, gain will be increased further. oon ode voltage gain, on the other hand, will be reduced since for coon ode operation the drain of is effectively connected to ground through 1/g 5, where g 5 is gate transconductance of M5. However, whenever we have capacitive load (actual or parasitic one) the increased output ipedance of the actively loaded differential pair would liit bandwidth of differential ode voltage gain. Parasitic capacitance in parallel with bias current source can degrade M even before starts to degrade. We will easure frequency response of differential aplifier with active load in lab. ctive load will be constructed out of two PMOS transistors of L115. M5 M6 V Figure 5. With active load the voltage gain of the differential aplifier with single ended input will be: r g r rm6 g. (7) V 3. PELIMINY LB in 3.1. onsider circuit in Figure 1. ssue = V = 5 V. ssue that and are both to be biased with 5 µ. Estiate the value of that would lead to the desired bias. Use paraeters of and fro prelab of laboratory. 3.. onsider circuit in Figure. ssue = V = 5 V and = 1 kω. ssue that and are both to be biased with 5 µ. Estiate the axiu aplitude of the input voltage that can be applied without driving FETs into nonsaturation? 3.3. onsider circuit in Figure 3. ssue = V = 5 V and = 1 kω. ssue that and are both to be biased with 5 µ. Use lab experiental value of the gate transconductance for both and. alculate the differential ode voltage gains for differential and single ended outputs. 3.4. onsider circuit in Figure 4b. ssue all paraeters fro 3.3. alculate the voltage gain defined as a ratio of to. 3.5. onsider circuit in Figure 5. ssue 5 µ biases for either of branches of differential pair. Estiate voltage gain ( / ) using your lab data obtained for S aplifier. 4
epartent of Electrical and oputer Engineering Fall 1 4. EXPEIMENT (pay attention that 4.1-4.4 easureents are fast but 4.5 can take tie) 4.1. sseble differential aplifier (Figure 1) using V = = 5 V and = 1 kω. Select 5 kω potentioeter and adjust it to obtain I bias = 5 µ. Make sure that all transistors are in saturation. Present the data confiring the saturation ode of -. 4.. Perfor easureents of the coon ode voltage gain using circuit fro Figure. Use sine wave input voltage with 1 khz frequency. djust input voltage aplitude to produce enough output signal but with no distortions. Measure both the single end and the differential output using oscilloscope. Present the data in the for of table. oent on results. 4.3. Perfor easureents of the differential ode voltage gain on the sae circuit. pply input signal as shown in Figure 4b but keep in both branches of differential pair. Measure both single end and differential output using oscilloscope. Present the data in the for of table. oent on results. alculate M using 4. and 4.3 data. 4.4. Measure the differential ode voltage gain for the circuit in Figure 4b, i.e. reove fro branch of circuit fro 4.3. opare with 4.3 easureent results. Explain your observations. 4.5. sseble circuit fro Figure 5. Measure the differential ode voltage gain at 1 khz. djust input signal aplitude to obtain undistorted output wavefor (you ight want to use voltage divider). Measure the corresponding coon ode voltage gain. Measure high 3dB frequency of differential and coon ode voltage gains and then for M. Present the data in the for of table. opare with 4.4 easureent results. Explain your observations. 4. EPOT The report should include the lab goals, short description of the work, the experiental and siulated data presented in plots, the data analysis and coparison followed by conclusions. Please follow the steps in the experiental part and clearly present all the results of easureents. Be creative; try to find soething interesting to coent on. 5