NXP P5CC052 Secure Contact PKI Smart Card Controller Analog Circuit Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2012 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. CAR-1201-902 21865DBHH Revision 1.0 Published: January 31, 2012 Revision 2.0 Published: March 30, 2012
Overview Introduction Brief Design Overview Component Descriptions Device Summary Figures To view, please click on the appropriate bookmark in the panel on the left. 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Die Markings 0.2.1 Die Photograph 0.2.2 Annotated Die Photograph 0.2.3 Die Photograph Metal 1 Layer 0.2.4 Die Architecture Metal 1 Layer 0.2.5 EEPROM Architecture Tables 1.0.0 ROM Content 2.0.0 Sub-Array to GBL and GDL Routing Schematics 1.0.0.0 Top Level Diagram 2.0.0.0 Voltage Regulator 2.1.0.0 Internal Voltage Supply Generator 2.1.1.0 Programmable Current Sink 2.1.2.0 NOR2 2.1.3.0 Level Shift 2.2.0.0 Reference Voltage Generator 1 2.3.0.0 Voltage Comparator 1 2.3.1.0 Amplifier 1 2.3.2.0 Level Shift 2.4.0.0 Internal Voltage Supply Detector 1 2.5.0.0 Internal Voltage Supply Detector 2 2.5.1.0 Internal Voltage Supply Detector Circuit 2.6.0.0 Unused Buffer Circuit
3.0.0.0 Bias Generator 3.1.0.0 Reference Voltage Generator 2 3.2.0.0 Voltage Generator 3.2.1.0 Voltage Follower 1 3.2.2.0 Voltage Follower 2 3.2.3.0 Voltage Follower 3 3.2.4.0 Amplifier 2 3.2.5.0 Bias Voltage Generator 1 3.2.5.1 Current Sink x1 3.2.5.2 Current Sink x4 3.2.5.3 Unused Current Sink 3.2.6.0 Bias Voltage Generator 2 3.2.6.1 Current Sink x2 3.3.0.0 Decoder 1 3.4.0.0 Programmable Current Generator 1 3.4.1.0 PMOS Bias Voltage Generator 3.4.2.0 PMOS Bias Voltage Generator 1 2 3.4.3.0 PMOS Bias Voltage Generator 1 4 3.4.4.0 PMOS Bias Voltage Generator 1 8 3.4.5.0 Unused PMOS Transistor 3.5.0.0 Bias Generator Circuit 1 3.6.0.0 Voltage Detector with Delay 3.7.0.0 Voltage Detector 1 3.7.1.0 Decoder 2 3.7.2.0 Programmable Voltage Generator 1 3.7.3.0 Amplifier 3 3.8.0.0 Internal Voltage Supply Detector 3 3.9.0.0 Voltage Detector 2 3.9.1.0 Comparator Bias Voltage Generator 3.9.2.0 Comparator 4.0.0.0 Internal Clock Generator 4.1.0.0 Ring Oscillator 1 4.2.0.0 Ring Oscillator 2 4.3.0.0 Saw Wave Generator 4.3.1.0 Amplifier 4
5.0.0.0 ADCs 5.1.0.0 ADC Enable Logic 5.2.0.0 Bias Current for ADCs 5.3.0.0 ADC 1 5.3.1.0 Voltage Divider 1 5.3.2.0 Amplifier 5 5.3.3.0 Amplifier 6 5.4.0.0 ADC 2 5.4.1.0 Voltage Divider 2 5.4.2.0 2 to 1 Mux 5.4.3.0 Amplifier 7 6.0.0.0 EEPROM 6.1.0.0 EEPROM Address Path 6.1.1.0 Row Decoder 6.1.1.1 AX01 Decoder 6.1.1.2 AX23 Decoder 6.1.1.3 AX45 Decoder 6.1.1.4 AX67 Decoder 6.1.1.5 AX89 Decoder 6.1.2.0 Row Driver Top 1 6.1.2.1 Row Driver - 4 Cells 6.1.2.2 Row Driver Cell 6.1.3.0 Row Driver Top 2 6.1.4.0 Column Decoder 6.1.4.1 AY01 Decoder 6.1.4.2 AY23 Decoder 6.1.5.0 Column Select Drivers (partial) 6.2.0.0 EEPROM Data Path 6.2.1.0 Memory Sub-array 6.2.2.0 Left Datapath - Bits to 7 6.2.2.1 Left Datapath 6.2.2.2 Page Buffer 6.2.2.3 DB Sense 6.2.2.4 DB Multiplexor 6.2.3.0 Left Error-Correcting Datapath - Bits 8 to 11 6.2.3.1 Left Error-Correcting Datapath 6.2.4.0 Left Data Detection 6.2.4.1 Data Detection Cell 6.2.5.0 Right Datapath - Bits 0 to 7
6.2.5.1 Right Datapath 6.2.6.0 Right Error-Correcting Datapath - Bits 8 to 11 6.2.6.1 Right Error-Correcting Datapath 6.2.7.0 Right Data Detection 6.2.8.0 GDB Multiplexor 6.2.9.0 DB_SEN Multiplexor 6.3.0.0 EEPROM Control 6.3.1.0 Array Control 6.3.2.0 Page Buffer Control 6.3.3.0 DB Control 6.3.4.0 DB Select Control 6.3.5.0 Enable Control 6.3.6.0 Standard Cell Digital Logic 1 6.3.6.1 Flip-Flop 6.3.7.0 Standard Cell Digital Logic 2 6.3.8.0 Clock Divider and Control Logic 6.4.0.0 Current References 6.5.0.0 EEPROM Array References 6.5.1.0 Array Voltage References 6.5.2.0 Voltage Reference Generator 6.5.3.0 Array Ground References - Pump Voltage Reference Generator 6.5.4.0 Voltage References 6.5.5.0 Current References 6.6.0.0 EEPROM Charge Pump 6.6.1.0 Sample and Hold 6.6.1.1 Clock Generator 6.6.1.2 Amplifier 6.6.2.0 Phase Gen and Charge Pump 6.6.2.1 Phase Generator for Positive Voltage Pump 6.6.2.2 Ring Oscillator 1 6.6.2.3 PMOS Charge Pump Cell 1 6.6.2.3 PMOS Charge Pump Cell 2 6.6.2.5 Phase Generator for Negative Voltage Pump 6.6.2.6 Ring Oscillator 2 6.6.2.7 NMOS Charge Pump Cell 1 6.6.2.8 NMOS Charge Pump Cell 2 6.6.2.9 Level Detector
7.0.0.0 Clock I/O 7.1.0.0 Clock Driver 7.1.1.0 Output Driver 7.1.1.1 High Side Driver 7.1.1.2 NOR2 7.1.1.3 Low Side Driver 7.2.0.0 Level Shift 2 7.3.0.0 Schmitt Inverter 7.4.0.0 ESD 8.0.0.0 I/Os 8.1.0.0 I/O1 Input Buffer 8.2.0.0 I/O3 Input Buffer 8.3.0.0 NCI I/O Buffer 8.3.1.0 Level Shift 8.3.2.0 NOR2 8.3.3.0 Schmitt Inverter 9.0.0.0 ESD Power Clamp 10.0.0.0 Multiplexers 10.1.0.0 Multiplexers Decoder 11.0.0.0 Logic 11.1.0.0 DFF Cell Library Signal Cross-Reference List About Chipworks
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