Fundamentals of Data Converters. DAVID KRESS Director of Technical Marketing

Fundamentals of Data Converters DAVID KRESS Director of Technical Marketing 9/14/2016

Analog to Electronic Signal Processing Sensor (INPUT) Amp Converter Digital Processor Actuator (OUTPUT) Amp Converter

Outline Sampled data system types Digitizing processes Data converters for measurement systems and errors Data converters for dynamic systems and errors Sampling system problems Structure and use of digital-analog converters Structure and use of analog-digital converters

Many Types of Sampled Data Systems Analog to digital converters Digital to analog converters Sample and hold amplifiers Peak detectors Comparators Switched cap filters Samples a continuous signal Domain conversion Analog to digital Digital to analog Continuous time to discrete time Continuous frequency to discrete frequency Sampling rate Continuous, discontinuous

Analog and Digital Domains Why Convert to Digital? Analog signals are continuous and provide the entire signal Digital signals capture only a portion of the signal Why digitize? Improved signal analysis potential More robust storage More accurate transmission Development objective of sampled data systems is to minimize effect of the sampling process

Sampled Data System: Sampling and Quantization f s f s f a LPF OR BPF N-BIT ADC DSP N-BIT DAC LPF OR BPF AMPLITUDE QUANTIZATION DISCRETE TIME SAMPLING f a t s = 1 f s t

Transfer Functions for Ideal 3-Bit DAC and ADC FS DAC ADC 111 110 ANALOG OUTPUT DIGITAL OUTPUT 101 100 QUANTIZATION UNCERTAINTY 011 010 001 QUANTIZATION UNCERTAINTY 000 001 010 011 100 101 110 111 ANALOG INPUT DIGITAL INPUT 000 FS

Unipolar Binary Code, 4-bit Converter BASE 10 NUMBER SCALE +10 V FS BINARY +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 +FS 1 LSB = 15/16 FS +7/8 FS +13/16 FS +3/4 FS +11/16 FS +5/16 FS +9/16 FS +1/2 FS +7/16 FS +3/8 FS +5/16 FS +1/4 FS +3/16 FS +1/8 FS 1 LSB = +1/16 FS 0 9.375 8.750 8.125 7.500 6.875 6.250 5.625 5.000 4.375 3.750 3.125 2.500 1.875 1.250 0.625 0.000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

Bipolar Codes, 4-bit Converter BASE 10 NUMBER +7 +6 +5 +4 +3 +2 +1 0 1 2 3 4 5 6 7 8 SCALE +FS 1LSB = +7/8 FS +3/4 FS +5/8 FS +1/2 FS +3/8 FS +1/4 FS +1/8 FS 0 1/8 FS 1/4 FS 3/8 FS 1/2 FS 5/8 FS 3/4 FS FS + 1LSB = 7/8 FS FS ±5V FS +4.375 +3.750 +3.125 +2.500 +1.875 +1.250 +0.625 0.000 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 CODES NOT NORMALLY USED IN COMPUTATIONS (SEE TEXT) OFFSET BINARY 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 TWOS COMP. 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 * ONES COMP. 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 *0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 ONES COMP. 0+ 0 0 0 0 0 1 1 1 1 SIGN MAG. 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 *1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 SIGN MAG. 0 0 0 0 1 0 0 0

Quantization: The Size of a Least Significant Bit (LSB) RESOLUTION N VOLTAGE (10V FS) ppm FS % FS db FS 2-bit 2 N 4 2.5 V 250,000 25 12 4-bit 16 625 mv 62,500 6.25 24 6-bit 64 156 mv 15,625 1.56 36 8-bit 256 39.1 mv 3,906 0.39 48 10-bit 1,024 9.77 mv (10 mv) 977 0.098 60 12-bit 4,096 2.44 mv 244 0.024 72 14-bit 16,384 610 V 61 0.0061 84 16-bit 65,536 153 V 15 0.0015 96 18-bit 262,144 38 V 4 0.0004 108 20-bit 1,048,576 9.54 V (10 V) 1 0.0001 120 22-bit 4,194,304 2.38 V 0.24 0.000024 132 24-bit 16,777,216 596 nv* 0.06 0.000006 144 *600nV is the Johnson Noise in a 10kHz BW of a 2.2k Resistor @ 25 C Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%. All other values may be calculated by powers of 2.

Practical Resolution Needs for Data Converters Instrumentation measurements Sensor resolution/accuracy of 0.5% = 1/200 8 bits equivalent to 1/256 -- digitizing will lose information 10x sensor resolution = 1/2000 -- 12 bits is 1/4096 Allows discrimination of small changes Can also be driven by display requirements Dynamic signal measurements Audio systems need better than 0.1% distortion at 5% of full scale Equivalent to 1/20,000 -- 16 bits is 1/65,536

Primary Errors in Data Converters Instrumentation and measurement Described in LSBs(least-significant-bit), % of FS, ppm of FS Offset error the input level needed to change the first code Gain/full-scale error the input level need to change the last code Nonlinearity deviation of codes from the line from zero to FS Differential nonlinearity code-to-code deviation from 1 LSB Transition noise ADC uncertainty in code center point

Transfer Functions for Non-Ideal 3-Bit DAC and ADC FS DAC ADC 111 110 ANALOG OUTPUT DIGITAL OUTPUT 101 100 MISSING CODE NON-MONOTONIC 011 010 001 000 001 010 011 100 101 110 111 DIGITAL INPUT 000 ANALOG INPUT FS

Combined Effects of Code Transition Noise and DNL CODE TRANSITION NOISE DNL TRANSITION NOISE AND DNL ADC OUTPUT CODE ADC INPUT ADC INPUT ADC INPUT

Primary Errors in Data Converters Dynamic systems SINAD (Signal-to-Noise-and-Distortion Ratio): The ratio of the rms signal amplitude to the mean value of the root-sumsquares (RSS) of all other spectral components, including harmonics, but excluding DC. ENOB (Effective Number of Bits): ENOB = SINAD 1.76dB 6.02dB SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio Without Harmonics: The ratio of the rms signal amplitude to the mean value of the root-sumsquares (RSS) of all other spectral components, excluding the first 5 harmonics and DC SFDR (Spurious-Free-Dynamic-Range) Signal dynamic range in the bandwidth of interest containing no frequency noise spurs

DIGITAL OUTPUT Quantization & Quantization Noise 111 110 101 100 011 010 001 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS NORMALIZED ANALOG INPUT Quantization Error Function quantization noise error: RMS value is LSB/3.464

Quantization Noise as a Function of Time +q 2 e(t) q 2 SLOPE = s t q 2s +q 2s ERROR = e(t) = st, q 2s < t < +q 2s MEAN-SQUARE ERROR = e 2 (t) = s q +q/2s (st) 2 dt = q/2s q 2 12 ROOT-MEAN-SQUARE ERROR = e 2 (t) = q 12

Ideal ADC Sampling 3 Different Frequencies, Sampled the Same

Ideal ADC Sampling Once Sampled, Information is Lost

Nyquist's Criteria A signal with a maximum frequency fa must be sampled at a rate fs > 2fa or information about the signal will be lost because of aliasing. Aliasing occurs whenever fs < 2fa A signal which has frequency components between fa and fb must be sampled at a rate fs > 2 (fb fa) in order to prevent alias components from overlapping the signal frequencies The concept of aliasing is widely used in communications applications such as direct IF-to-digital conversion.

Aliasing occurs in Many Domains Spatial, Temporal, etc. Image Source : Wikipedia

Sampling & Aliasing in the Time Domain ALIASED SIGNAL = f s f a INPUT = f a 1 f s t NOTE: f a IS SLIGHTLY LESS THAN f s

Baseband Antialiasing Filter Requirements f a A fs - f a f a B Kf s - f a DR Anti-Alias Filter Prevents Aliasing Contributes to Dynamic Range Anti-Alias Filter Objectives Brick Wall (Steep/Deep Rolloff) Linear Passband Linear Phase f s 2 STOPBAND ATTENUATION = DR TRANSITION BAND: f a to f s - f a CORNER FREQUENCY: f a f s Kf s 2 STOPBAND ATTENUATION = DR TRANSITION BAND: f a to Kf s - f a CORNER FREQUENCY: f a Kf s

Oversampling Relaxes Requirements on Baseband Antialiasing Filter A B f f Kf s - f a fs - f a a a DR f s 2 f s STOPBAND ATTENUATION = DR TRANSITION BAND: f a to f s - f a CORNER FREQUENCY: f a Kf s 2 STOPBAND ATTENUATION = DR TRANSITION BAND: f a to Kf s - f a CORNER FREQUENCY: f a Kf s

Sample-and-Hold Function Required for Digitizing AC Signals SAMPLING CLOCK TIMING ANALOG INPUT SW CONTROL C ADC ENCODER N ENCODER CONVERTS DURING HOLD TIME HOLD SW CONTROL SAMPLE SAMPLE

Input Frequency Limitations of Non-Sampling ADC (Encoder) v(t) = ANALOG INPUT 2 q N sin (2 f t ) 2 N-BIT SAR ADC ENCODER CONVERSION TIME = 8µs N dv dt = q 2 N 2 2 f cos (2 f t ) f s = 100 ksps dv dt max f max = q = 2 (N 1) 2 f dv dt max 2 (N 1) 2 q EXAMPLE: dv = 1 LSB = q dt = 8µs N = 12, 2 N = 4096 f max = dv dt max q 2 N f max = 9.7 Hz

Effective Aperture Delay Time Measured with Respect to ADC Input +FS ANALOG INPUT SINEWAVE ZERO CROSSING 0V -FS +t ' t e e ' SAMPLING CLOCK t e '

Effects of Aperture Jitter and Sampling Clock Jitter ANALOG INPUT D v = dv Dt dt dv dt = SLOPE D v = APERTURE JITTER ERROR RMS NOMINAL HELD OUTPUT D t = APERTURE JITTER RMS HOLD TRACK

Theoretical SNR and ENOB Due to Jitter vs. Fullscale Sinewave Analog Input Frequency 120 t j = 0.1ps t j = 50fs SNR = 20log 10 1 2 ft j 18 100 t j = 1ps 16 14 SNR (db) 80 60 t j = 10ps t j = 100ps 12 10 ENOB 8 40 t j = 1ns 6 20 1 3 10 30 100 FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz) 4

1-Bit DAC: Changeover Switch (SPDT) V REF OUTPUT

Simplest Voltage Output Thermometer DAC: The Kelvin Divider ( AKA - "String DAC") V REF R R R R R 3-TO-8 DECODER 8 TO SWITCHES 3-BIT DIGITAL INPUT ANALOG OUTPUT R R R

The Simplest Current Output Thermometer (Fully-Decoded) DAC V REF R R R R R R R 3-TO-7 DECODER 7 TO SWITCHES CURRENT OUTPUT INTO VIRTUAL GROUND (USUALLY AN OP-AMP I-V CONVERTER) 3-BIT DIGITAL INPUT

Voltage-Mode Binary Weighted Resistor DAC V OUT R/8 R/4 R/2 R LSB MSB V REF

Current-Mode R-2R Ladder Network Resistor-Based DAC V REF * R R R << R 2R 2R 2R 2R 2R MSB LSB CURRENT OUTPUT INTO VIRTUAL GROUND * GAIN TRIM IF REQUIRED

Segmented Voltage Output DACs V REF (A) KELVIN-VARLEY DIVIDER ("STRING DAC") A B A V REF (B) KELVIN DIVIDER AND R-2R LADDER NETWORK OUTPUT B A B A OUTPUT B A B A A B NOTE: MSB OF R-2R LADDER ON RIGHT IF THE R-2R LADDER NETWORK IS MONOTONIC, THE WHOLE DAC IS MONOTONIC

08344-001 Circuits from the Lab Multiplying DAC attenuates AC signal +10V VIN 10V R1 R1 RCOM R2 REF ROFS ROFS RFB RFB C8 2.2pF +12V C4 0.1µF +5V C1 1µF C2 0.1µF 16/14 DATA VDD U1 AD5546/AD5556 16/14-BIT GND IOUT C5 1µF V+ U2 AD8610 V + C6 0.1µF VOUT WR LDAC RS MSB WR LDAC RS MSB 12V C7 1µF

Digital Potentiometer Applications Amplifier and other component adjustment Connect across offset-adjust pins Gain adjustment or fine tuning System calibration Digital pots inserted in strategic system locations System tune-up automatically or manually Non-volatile RAM setting returns on system power-up RAM can be one-time program or re-programmable Settings can be stored centrally and transmitted for system re-adjustment

Circuits from the Lab Digital Potentiometer Gain Adjustment

1-Bit DAC: Highly-sophisticated Digital-Audio DAC V REF OUTPUT

Sampled Data System: Sampling and Quantization

Basic ADC with External Reference SAMPLING CLOCK V DD V REF ANALOG INPUT ADC DIGITAL OUTPUT EOC, DATA READY, ETC. V SS GROUND (MAY BE INTERNALLY CONNECTED TO V SS )

The Comparator: A 1-Bit ADC LATCH ENABLE DIFFERENTIAL ANALOG INPUT + LOGIC OUTPUT COMPARATOR OUTPUT "1" V HYSTERESIS "0" 0 DIFFERENTIAL ANALOG INPUT

Basic Successive Approximation ADC (Feedback Subtraction ADC) CONVERT START ANALOG INPUT SHA COMPARATOR DAC TIMING CONTROL LOGIC: SUCCESSIVE APPROXIMATION REGISTER (SAR) EOC, DRDY, OR BUSY OUTPUT

Successive Approximation ADC Algorithm Analogy Using Binary Weights TEST ASSUME X = 45 IS X 32? YES RETAIN 32 1 IS X (32 +16)? NO REJECT 16 0 IS X (32 +8)? YES RETAIN 8 1 IS X (32 +8 + 4)? YES RETAIN 4 1 IS X (32 +8 + 4 + 2)? NO REJECT 2 0 IS X (32 +8 + 4 + 2 + 1)? YES RETAIN 1 1 TOTALS: X = 32 + 8 + 4 + 1 = 45 10 = 101101 2

3-bit All-Parallel (Flash) Converter STROBE ANALOG INPUT + +V REF 1.5R R + R + R + PRIORITY ENCODER AND LATCH N DIGITAL OUTPUT R + R + R + 0.5R

Sigma-Delta ADC - First-Order Modulator INTEGRATOR CLOCK Kf s f s V IN + + _ B A +V REF _ LATCHED COMPARATOR (1-BIT ADC) DIGITAL FILTER AND DECIMATOR N-BITS f s 1-BIT DAC V REF 1-BIT DATA STREAM 1-BIT, Kf s SIGMA-DELTA MODULATOR

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