Preferred Device Power MOSFET 2 Amps, 3 Volts, Logic Level NChannel This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Features Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits I DSS and V DS(on) Specified at Elevated Temperature PbFree Packages are Available MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit DrainSource Voltage V DSS 3 DrainGate Voltage (R GS = 1. M ) V DGR 3 GateSource Voltage Continuous NonRepetitive (t p ms) Drain Current Continuous Drain Current Continuous @ C Drain Current Single Pulse (t p s) Total Power Dissipation Derate above 25 C Total Power Dissipation @ T C = 25 C (Note 2) V GS ±15 V GSM ± 2 I D I D I DM 2 16 6 P D 7.6 1.75 Operating and Storage Temperature Range T J, T stg 55 to 15 Single Pulse DraintoSource Avalanche Energy Starting T J = 25 C (V DD = 25, V GS = 5., Peak I L = 2 Apk, L = 1. mh, R G = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1) JunctiontoAmbient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for seconds Vpk Adc Apk W W/ C C E AS 2 mj R JC R JA R JA 1.67 71. C/W T L 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR board using the minimum recommended pad size. 2. When surface mounted to an FR board using the.5 sq.in. drain pad size. V (BR)DSS 1 2 3 G CASE 369C STYLE 2 3 V 3 m 5. V 1 2 3 CASE 369D STYLE 2 Y WW 2N3HL G R DS(on) TYP NChannel D Preferred devices are recommended choices for future use and best overall value. S 1 Gate 2 Drain 2 Drain 3 Source 1 Gate 3 Source YWW 2N 3HLG YWW 2N 3HL = Year = Work Week = Device Code = PbFree Package I D MAX 2 A (Note 1) MARKING DIAGRAM & PIN ASSIGNMENTS Drain Drain ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 26 June, 26 Rev. 6 1 Publication Order Number: MTD2N3HDL/D
ELECTRICAL CHARACTERISTICS (T J = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS DraintoSource Breakdown Voltage (C pk 2.) (Note 5) (V GS =, I D = 25 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (V DS = 3, V GS = ) (V DS = 3, V GS =, T J = 125 C) GateBody Leakage Current (V GS = ±15, V DS = ) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (C pk 2.) (Note 5) (V DS = V GS, I D = 25 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (C pk 2.) (Note 5) (V GS =., I D = Adc) (V GS = 5., I D = Adc) DraintoSource OnVoltage (V GS = 5. ) (I D = 2 Adc) (I D = Adc, T J = 125 C) Forward Transconductance (V DS = 5., I D = Adc) V (BR)DSS 3 I DSS 3 I GSS V GS(th) 1. 1.5 5. DS(on).3.3 V DS(on).55 2...35.8.7 g FS 13 mv/ C Adc nadc mv/ C mhos DYNAMIC CHARACTERISTICS Input Capacitance C iss 88 126 pf Output Capacitance (V DS = 25, V GS =, f = 1. MHz) C oss 3 2 Transfer Capacitance C rss 8 15 SWITCHING CHARACTERISTICS (Note ) TurnOn Delay Time t d(on) 13 2 ns Rise Time (V DD = 15, I D = 2 Adc, t r 212 238 TurnOff Delay Time V GS = 5., R G = 9.1 ) t d(off) 23 Fall Time t f 8 Gate Charge (See Figure 8) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (C pk 2.) (Note 5) Reverse Recovery Time (See Figure 15) Reverse Recovery Stored Charge (V DS = 2, I D = 2 Adc, V GS = 5. ) (I S = 2 Adc, V GS = ) (I S = 2 Adc, V GS =, T J = 125 C) (I S = 2 Adc, V GS =, di S /dt = A/ s) INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead.25 from package to center of die) Internal Source Inductance (Measured from the source lead.25 from package to source bond pad) 3. Pulse Test: Pulse Width 3 s, Duty Cycle 2%.. Switching characteristics are independent of operating junction temperature. 5. Reflects typical values. C pk = Absolute Value of Spec (SpecAVG/3.516 A). Q T 13. 18.9 nc Q 1 3. Q 2 7.3 Q 3 6. V SD.95.87 1.1 t rr 33 ns t a 23 t b Q RR 33 C L D.5 L S 7.5 nh nh 2
TYPICAL ELECTRICAL CHARACTERISTICS I D, DRAIN CURRENT (AMPS) T J = 25 C V GS = V 5 V.5 V V DS V 3 2 8 V.2..6.8 1. 1.2 1. 1.6 1.8 2. 6 V V DS, DRAINTOSOURCE VOLTAGE (Volts) V 3.5 V 3 V 2.5 V I D, DRAIN CURRENT (AMPS) 3 2 C 25 C T J = 55 C 1. 1. 1.8 2.2 2.6 3. 3. 3.8.2.6 5. V GS, GATETOSOURCE VOLTAGE (Volts) Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics RDS(on), DRAINTOSOURCE RESISTANCE (OHMS).52 V GS = 5 V. T J = C.36 25 C.28 55 C RDS(on), DRAINTOSOURCE RESISTANCE (OHMS).36 T J = 25 C.32 V GS = 5 V.28.2 V.2.2 8 16 2 32 8 16 2 32 I D, DRAIN CURRENT (Amps) I D, DRAIN CURRENT (Amps) Figure 3. OnResistance versus Drain Current and Temperature Figure. OnResistance versus Drain Current and Gate Voltage R DS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1. 1.2 1..8 V GS = 5 V I D = A.6 5 25 25 5 75 125 15 T J, JUNCTION TEMPERATURE ( C) I DSS, LEAKAGE (na) 1 V GS = V T J = 125 C C 25 C 6 12 18 2 3 V DS, DRAINTOSOURCE VOLTAGE (Volts) Figure 5. OnResistance Variation with Temperature Figure 6. DrainToSource Leakage Current versus Voltage 3
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I G(AV) ) can be made from a rudimentary analysis of the drive circuit so that t = Q/I G(AV) During the rise and fall time interval when switching a resistive load, V GS remains virtually constant at a level known as the plateau voltage, V SGP. Therefore, rise and fall times may be approximated by the following: t r = Q 2 x R G /(V GG V GSP ) t f = Q 2 x R G /V GSP where V GG = the gate drive voltage, which varies from zero to V GG R G = the gate drive resistance and Q 2 and V GSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: t d(on) = R G C iss In [V GG /(V GG V GSP )] t d(off) = R G C iss In (V GG /V GSP ) The capacitance (C iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 28 2 V DS = V V GS = V T J = 25 C C, CAPACITANCE (pf) 2 16 12 8 C iss C rss C iss C rss C oss 5 5 15 2 25 V GS V DS GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts) Figure 7. Capacitance Variation
V GS, GATETOSOURCE VOLTAGE (VOLTS) 1 28 12 8 QT 6 12 Q1 Q2 8 I D = 2 A 2 T J = 25 C Q3 V DS 2 6 8 12 1 Q G, TOTAL GATE CHARGE (nc) V GS 2 2 16 V DS, DRAINTOSOURCE VOLTAGE (VOLTS) t, TIME (ns) V DD = 15 V I D = 2 A V GS = 5. V T J = 25 C t r t f t d(off) t d(on) 1 R G, GATE RESISTANCE (Ohms) Figure 8. GateToSource and DrainToSource Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr, due to the storage of minority carrier charge, Q RR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short t rr and low Q RR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diode s negative di/dt during t a is directly controlled by the device clearing the stored charge. However, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. IS, SOURCE CURRENT (AMPS) 2 16 12 8 V GS = V T J = 25 C.5.55.6.65.7.75.8.85.9.95 V SD, SOURCETODRAIN VOLTAGE (Volts) 1. Figure. Diode Forward Voltage versus Current 5
I S, SOURCE CURRENT di/dt = 3 A/ s Standard Cell Density t rr High Cell Density t rr t b t a t, TIME Figure 11. Reverse Recovery Time (t rr ) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25 C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, t f ) does not exceed s. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R JC ). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (I DM ), the energy rating is specified at rated continuous current (I D ), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous I D can safely be assumed to equal the values indicated. I D, DRAIN CURRENT (AMPS) V GS = 2 V SINGLE PULSE T C = 25 C s 1 ms ms R DS(on) LIMIT THERMAL LIMIT dc PACKAGE LIMIT 1.1 1. V DS, DRAINTOSOURCE VOLTAGE (VOLTS) Figure 12. Maximum Rated Forward Biased Safe Operating Area E AS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mj) 2 16 12 8 25 5 75 125 T J, STARTING JUNCTION TEMPERATURE ( C) I D = 2 A Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature 15 6
TYPICAL ELECTRICAL CHARACTERISTICS r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1..1.1 1.E5 D =.5.2.1.5.2.1 SINGLE PULSE t, TIME (s) P (pk) t 1 t 2 DUTY CYCLE, D = t 1 /t 2 R JC (t) = r(t) R JC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t 1 T J(pk) T C = P (pk) R JC (t) 1.E 1.E3 1.E2 1.E1 1.E+ 1.E+1 Figure 1. Thermal Response I S di/dt t rr t a t b TIME t p.25 I S I S Figure 15. Diode Reverse Recovery Waveform ORDERING INFORMATION Device Package Shipping MTD2N3HDL 75 Units / Rail MTD2N3HDLG (PbFree) 75 Units / Rail MTD2N3HDL1 Straight Lead 75 Units / Rail MTD2N3HDLT 25 / Tape & Reel MTD2N3HDLTG (PbFree) 25 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. 7
PACKAGE DIMENSIONS CASE 369C1 ISSUE O B C T SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y1.5M, 1982. 2. CONTROLLING DIMENSION: INCH. V S F R 1 2 3 G L A K D 2 PL J H.13 (.5) M T E U Z INCHES MILLIMETERS DIM MIN MAX MIN MAX A.235.25 5.97 6.22 B.25.265 6.35 6.73 C.86.9 2.19 2.38 D.27.35.69.88 E.18.23.6.58 F.37.5.9 1.1 G.18 BSC.58 BSC H.3..87 1.1 J.18.23.6.58 K.2.11 2.6 2.89 L.9 BSC 2.29 BSC R.18.215.57 5.5 S.25..63 1.1 U.2.51 V.35.5.89 1.27 Z.155 3.93 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE. DRAIN SOLDERING FOOTPRINT* 6.2.2 2.58.1 3..118 5.8.228 1.6.63 6.172.23 SCALE 3:1 mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8
PACKAGE DIMENSIONS 3 (SINGLE GAUGE) CASE 369D1 ISSUE B V B R C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y1.5M, 1982. 2. CONTROLLING DIMENSION: INCH. S T SEATING PLANE F 1 2 3 G A K D 3 PL J.13 (.5) M T H Z INCHES MILLIMETERS DIM MIN MAX MIN MAX A.235.25 5.97 6.35 B.25.265 6.35 6.73 C.86.9 2.19 2.38 D.27.35.69.88 E.18.23.6.58 F.37.5.9 1.1 G.9 BSC 2.29 BSC H.3..87 1.1 J.18.23.6.58 K.35.38 8.89 9.65 R.18.215.5 5.5 S.25..63 1.1 V.35.5.89 1.27 Z.155 3.93 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: 336752175 or 83386 Toll Free USA/Canada Fax: 336752176 or 833867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 82829855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 21 33 79 29 Japan Customer Focus Center Phone: 8135773385 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MTD2N3HDL/D